- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨�(m菐i)璩�(m脿i)IC缍�(w菐ng) > PDF鐩寗3817 > PIC18F4620-I/P (Microchip Technology)IC MCU FLASH 32KX16 40DIP PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | PIC18F4620-I/P |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 179/286闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MCU FLASH 32KX16 40DIP |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Asynchronous Stimulus 8-bit PIC® Microcontroller Portfolio |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 10 |
| 绯诲垪锛� | PIC® 18F |
| 鏍稿績铏曠悊鍣細 | PIC |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 40MHz |
| 閫ｉ€氭€э細 | I²C锛孲PI锛孶ART/USART |
| 澶栧湇瑷�(sh猫)鍌欙細 | 娆犲妾㈡脯(c猫)/寰�(f霉)浣嶏紝HLVD锛孭OR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 36 |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 | 64KB锛�32K x 16锛� |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄩ(l猫i)鍨嬶細 | 闁冨瓨 |
| EEPROM 澶�?銆�?/td> | 1K x 8 |
| RAM 瀹归噺锛� | 3.8K x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 4.2 V ~ 5.5 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 13x10b |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 40-DIP锛�0.600"锛�15.24mm锛� |
| 鍖呰锛� | 绠′欢 |
| 鐢�(ch菐n)鍝佺洰閷勯爜(y猫)闈細 | 644 (CN2011-ZH PDF) |
| 閰嶇敤锛� | DM163026-ND - BOARD DEMO LOW POWER SOLUTIONS I3DB18F4620-ND - BOARD DAUGHTER ICEPIC3 DVA18XP400-ND - DEVICE ADAPTER 18F4220 PDIP 40LD 444-1001-ND - DEMO BOARD FOR PICMICRO MCU ACICE0206-ND - ADAPTER MPLABICE 40P 600 MIL |
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PIC18C601/801
DS39541A-page 290
Advance Information
2001 Microchip Technology Inc.
TABLE 22-19: MASTER SSP I2C BUS DATA REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Max
Units
Conditions
100
THIGH
Clock high time
100 kHz mode
2(TOSC)(BRG + 1)
鈥�
ms
400 kHz mode
2(TOSC)(BRG + 1)
鈥�
ms
1 MHz mode(1)
2(TOSC)(BRG + 1)
鈥�
ms
101
TLOW
Clock low time
100 kHz mode
2(TOSC)(BRG + 1)
鈥�
ms
400 kHz mode
2(TOSC)(BRG + 1)
鈥�
ms
1 MHz mode(1)
2(TOSC)(BRG + 1)
鈥�
ms
102
TR
SDA and SCL
rise time
100 kHz mode
鈥�
1000
ns
Cb is specified to be
from 10 to 400 pF
400 kHz mode
20 + 0.1Cb
300
ns
1 MHz mode(1)
鈥�
300
ns
103
TF
SDA and SCL
fall time
100 kHz mode
鈥�
300
ns
Cb is specified to be
from 10 to 400 pF
400 kHz mode
20 + 0.1Cb
300
ns
1 MHz mode(1)
鈥�
100
ns
90
TSU:STA
START condition
setup time
100 kHz mode
2(TOSC)(BRG + 1)
鈥�
ms
Only relevant for
Repeated START
condition
400 kHz mode
2(TOSC)(BRG + 1)
鈥�
ms
1 MHz mode(1)
2(TOSC)(BRG + 1)
鈥�
ms
91
THD:STA
START condition
hold time
100 kHz mode
2(TOSC)(BRG + 1)
鈥�
ms
After this period, the first
clock pulse is generated
400 kHz mode
2(TOSC)(BRG + 1)
鈥�
ms
1 MHz mode(1)
2(TOSC)(BRG + 1)
鈥�
ms
106
THD:DAT
Data input
hold time
100 kHz mode
0
鈥�
ns
400 kHz mode
0
0.9
ms
1 MHz mode(1)
TBD
鈥�
ns
107
TSU:DAT
Data input
setup time
100 kHz mode
250
鈥�
ns
(Note 2)
400 kHz mode
100
鈥�
ns
1 MHz mode(1)
TBD
鈥�
ns
92
TSU:STO
STOP condition
setup time
100 kHz mode
2(TOSC)(BRG + 1)
鈥�
ms
400 kHz mode
2(TOSC)(BRG + 1)
鈥�
ms
1 MHz mode(1)
2(TOSC)(BRG + 1)
鈥�
ms
109
TAA
Output valid from
clock
100 kHz mode
鈥�
3500
ns
400 kHz mode
鈥�
1000
ns
1 MHz mode(1)
鈥斺€�
ns
110
TBUF
Bus free time
100 kHz mode
4.7
鈥�
ms
Time the bus must be
free before a new
transmission can start
400 kHz mode
1.3
鈥�
ms
1 MHz mode(1)
TBD
鈥�
ms
D102
Cb
Bus capacitive loading
鈥�
400
pF
Note 1: Maximum pin capacitance = 10 pF for all I2C pins.
鈮� 250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line. Before the SCL line is released, parameter #102 + parameter
#107 = 1000 + 250 = 1250 ns (for 100 kHz mode).
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
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| 1-533082-0 | CONN PIN HDI UNPLATED |
| 535875-1 | CONN GUIDE PIN/POWER RCPT TBC |
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| PIC18F4620T-I/ML | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 64KB 3968 RAM 36 I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| PIC18F4620T-I/PT | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 64KB 3968 RAM 36 I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| PIC18F4680-E/ML | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 64KB 3328 RAM w/ECAN RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| PIC18F4680-E/P | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 64KB 3328 RAM w/ECAN RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| PIC18F4680-E/PT | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 64KB 3328 RAM w/ECAN RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
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