TABLE 17-11: I2C BUS DATA " />
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  • 鍙冩暩(sh霉)璩囨枡
    鍨嬭櫉锛� PIC18F4610T-I/ML
    寤犲晢锛� Microchip Technology
    鏂囦欢闋佹暩(sh霉)锛� 106/234闋�
    鏂囦欢澶�?銆�?/td> 0K
    鎻忚堪锛� IC MCU FLASH 32KX16 44QFN
    妯�(bi膩o)婧�(zh菙n)鍖呰锛� 1,600
    绯诲垪锛� PIC® 18F
    鏍稿績铏曠悊鍣細 PIC
    鑺珨灏哄锛� 8-浣�
    閫熷害锛� 40MHz
    閫i€氭€э細 I²C锛孲PI锛孶ART/USART
    澶栧湇瑷�(sh猫)鍌欙細 娆犲妾㈡脯/寰�(f霉)浣嶏紝HLVD锛孭OR锛孭WM锛學DT
    杓稿叆/杓稿嚭鏁�(sh霉)锛� 36
    绋嬪簭瀛樺劜鍣ㄥ閲忥細 64KB锛�32K x 16锛�
    绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 闁冨瓨
    RAM 瀹归噺锛� 3.8K x 8
    闆诲 - 闆绘簮 (Vcc/Vdd)锛� 4.2 V ~ 5.5 V
    鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 13x10b
    鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
    宸ヤ綔婧害锛� -40°C ~ 85°C
    灏佽/澶栨锛� 44-VQFN 瑁搁湶鐒婄洡
    鍖呰锛� 甯跺嵎 (TR)
    绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�绗�80闋�绗�81闋�绗�82闋�绗�83闋�绗�84闋�绗�85闋�绗�86闋�绗�87闋�绗�88闋�绗�89闋�绗�90闋�绗�91闋�绗�92闋�绗�93闋�绗�94闋�绗�95闋�绗�96闋�绗�97闋�绗�98闋�绗�99闋�绗�100闋�绗�101闋�绗�102闋�绗�103闋�绗�104闋�绗�105闋�鐣�(d膩ng)鍓嶇106闋�绗�107闋�绗�108闋�绗�109闋�绗�110闋�绗�111闋�绗�112闋�绗�113闋�绗�114闋�绗�115闋�绗�116闋�绗�117闋�绗�118闋�绗�119闋�绗�120闋�绗�121闋�绗�122闋�绗�123闋�绗�124闋�绗�125闋�绗�126闋�绗�127闋�绗�128闋�绗�129闋�绗�130闋�绗�131闋�绗�132闋�绗�133闋�绗�134闋�绗�135闋�绗�136闋�绗�137闋�绗�138闋�绗�139闋�绗�140闋�绗�141闋�绗�142闋�绗�143闋�绗�144闋�绗�145闋�绗�146闋�绗�147闋�绗�148闋�绗�149闋�绗�150闋�绗�151闋�绗�152闋�绗�153闋�绗�154闋�绗�155闋�绗�156闋�绗�157闋�绗�158闋�绗�159闋�绗�160闋�绗�161闋�绗�162闋�绗�163闋�绗�164闋�绗�165闋�绗�166闋�绗�167闋�绗�168闋�绗�169闋�绗�170闋�绗�171闋�绗�172闋�绗�173闋�绗�174闋�绗�175闋�绗�176闋�绗�177闋�绗�178闋�绗�179闋�绗�180闋�绗�181闋�绗�182闋�绗�183闋�绗�184闋�绗�185闋�绗�186闋�绗�187闋�绗�188闋�绗�189闋�绗�190闋�绗�191闋�绗�192闋�绗�193闋�绗�194闋�绗�195闋�绗�196闋�绗�197闋�绗�198闋�绗�199闋�绗�200闋�绗�201闋�绗�202闋�绗�203闋�绗�204闋�绗�205闋�绗�206闋�绗�207闋�绗�208闋�绗�209闋�绗�210闋�绗�211闋�绗�212闋�绗�213闋�绗�214闋�绗�215闋�绗�216闋�绗�217闋�绗�218闋�绗�219闋�绗�220闋�绗�221闋�绗�222闋�绗�223闋�绗�224闋�绗�225闋�绗�226闋�绗�227闋�绗�228闋�绗�229闋�绗�230闋�绗�231闋�绗�232闋�绗�233闋�绗�234闋�
    PIC16F87XA
    DS39582B-page 192
    2003 Microchip Technology Inc.
    TABLE 17-11: I2C BUS DATA REQUIREMENTS
    Param
    No.
    Sym
    Characteristic
    Min
    Max
    Units
    Conditions
    100
    THIGH
    Clock High Time
    100 kHz mode
    4.0
    鈥�
    s
    400 kHz mode
    0.6
    鈥�
    s
    SSP Module
    0.5 TCY
    鈥�
    101
    TLOW
    Clock Low Time
    100 kHz mode
    4.7
    鈥�
    s
    400 kHz mode
    1.3
    鈥�
    s
    SSP Module
    0.5 TCY
    鈥�
    102
    TR
    SDA and SCL Rise
    Time
    100 kHz mode
    鈥�
    1000
    ns
    400 kHz mode
    20 + 0.1 CB
    300
    ns
    Cb is specified to be from 10 to
    400 pF
    103
    TF
    SDA and SCL Fall
    Time
    100 kHz mode
    鈥�
    300
    ns
    400 kHz mode
    20 + 0.1 CB
    300
    ns
    CB is specified to be from 10 to
    400 pF
    90
    TSU:STA
    Start Condition Setup
    Time
    100 kHz mode
    4.7
    鈥�
    s
    Only relevant for Repeated Start
    condition
    400 kHz mode
    0.6
    鈥�
    s
    91
    THD:STA
    Start Condition Hold
    Time
    100 kHz mode
    4.0
    鈥�
    s
    After this period, the first clock
    pulse is generated
    400 kHz mode
    0.6
    鈥�
    s
    106
    THD:DAT
    Data Input Hold Time
    100 kHz mode
    0
    鈥�
    ns
    400 kHz mode
    0
    0.9
    s
    107
    TSU:DAT
    Data Input Setup Time 100 kHz mode
    250
    鈥�
    ns
    (Note 2)
    400 kHz mode
    100
    鈥�
    ns
    92
    TSU:STO
    Stop Condition Setup
    Time
    100 kHz mode
    4.7
    鈥�
    s
    400 kHz mode
    0.6
    鈥�
    s
    109
    TAA
    Output Valid from
    Clock
    100 kHz mode
    鈥�
    3500
    ns
    (Note 1)
    400 kHz mode
    鈥�
    ns
    110
    TBUF
    Bus Free Time
    100 kHz mode
    4.7
    鈥�
    s
    Time the bus must be free before
    a new transmission can start
    400 kHz mode
    1.3
    鈥�
    s
    CB
    Bus Capacitive Loading
    鈥�
    400
    pF
    Note
    1:
    As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns)
    of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
    2:
    A fast mode (400 kHz) I2C bus device can be used in a standard mode (100 kHz) I2C bus system, but the requirement
    that, TSU:DAT
    鈮� 250 ns, must then be met. This will automatically be the case if the device does not stretch the LOW
    period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit
    to the SDA line, TR MAX. + TSU:DAT = 1000 + 250 = 1250 ns (according to the standard mode I2C bus specification),
    before the SCL line is released.
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