參數(shù)資料
型號: PIC18F458-I/PT
廠商: Microchip Technology
文件頁數(shù): 76/116頁
文件大?。?/td> 0K
描述: IC MCU CAN FLSH 16K 40MHZ 44TQFP
產(chǎn)品培訓模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標準包裝: 160
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 40MHz
連通性: CAN,I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復位,LVD,POR,PWM,WDT
輸入/輸出數(shù): 33
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 1.5K x 8
電壓 - 電源 (Vcc/Vdd): 4.2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤
配用: XLT44PT3-ND - SOCKET TRAN ICE 44MQFP/TQFP
AC164305-ND - MODULE SKT FOR PM3 44TQFP
444-1001-ND - DEMO BOARD FOR PICMICRO MCU
AC164020-ND - MODULE SKT PROMATEII 44TQFP
PIC18FXX8
DS41159E-page 60
2006 Microchip Technology Inc.
REGISTER 5-1:
EECON1: EEPROM CONTROL REGISTER 1
R/W-x
U-0
R/W-0
R/W-x
R/W-0
R/S-0
EEPGD
CFGS
FREE
WRERR
WREN
WR
RD
bit 7
bit 0
bit 7
EEPGD: Flash Program or Data EEPROM Memory Select bit
1
= Access program Flash memory
0
= Access data EEPROM memory
bit 6
CFGS: Flash Program/Data EE or Configuration Select bit
1
= Access Configuration registers
0
= Access program Flash or data EEPROM memory
bit 5
Unimplemented: Read as ‘0’
bit 4
FREE: Flash Row Erase Enable bit
1
= Erase the program memory row addressed by TBLPTR on the next WR command
(reset by hardware)
0
= Perform write only
bit 3
WRERR: Write Error Flag bit
1
= A write operation is prematurely terminated
(any MCLR or any WDT Reset during self-timed programming in normal operation)
0
= The write operation completed
Note:
When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allows
tracing of the error condition.
bit 2
WREN: Write Enable bit
1
= Allows write cycles
0
= Inhibits write to the EEPROM or Flash memory
bit 1
WR: Write Control bit
1
= Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle
WR bit can only be set (not cleared) in software.)
0
= Write cycle is complete
bit 0
RD: Read Control bit
1
= Initiates an EEPROM read
(Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared)
in software. RD bit cannot be set when EEPGD = 1.)
0
= Does not initiate an EEPROM read
Legend:
R = Readable bit
W = Writable bit
S = Settable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
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