鈥� Baud Rate register The baud rate (BAUD) register d" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� PIC18F4450T-I/PT
寤�(ch菐ng)鍟嗭細 Microchip Technology
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鍖呰锛� 甯跺嵎 (TR)
閰嶇敤锛� DM163025-ND - PIC DEM FULL SPEED USB DEMO BRD
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218
XMEGA A [MANUAL]
8077I鈥揂VR鈥�11/2012
19.9.5 BAUD
鈥� Baud Rate register
The baud rate (BAUD) register defines the relation between the system clock and the TWI bus clock (SCL) frequency.
The frequency relation can be expressed by using the following equation:
[1]
The BAUD register must be set to a value that results in a TWI bus clock frequency (fTWI) equal or less than 100kHz or
400kHz, depending on which standard the application should comply with. The following equation [2] expresses equation
[1] solved for the BAUD value:
[2]
The BAUD register should be written only while the master is disabled.
19.9.6 ADDR
鈥� Address register
When the address (ADDR) register is written with a slave address and the R/W bit while the bus is idle, a START
condition is issued and the 7-bit slave address and the R/W bit are transmitted on the bus. If the bus is already owned
when ADDR is written, a repeated START is issued. If the previous transaction was a master read and no acknowledge
is sent yet, the acknowledge action is sent before the repeated START condition.
After completing the operation and the acknowledge bit from the slave is received, the SCL line is forced low if arbitration
was not lost. WIF is set.
If the bus state is unknown when ADDR is written, WIF is set and BUSERR is set.
All TWI master flags are automatically cleared when ADDR is written. This includes BUSERR, ARBLOST, RIF, and WIF.
The master ADDR can be read at any time without interfering with ongoing bus activity.
19.9.7 DATA
鈥� Data register
The data (DATA) register is used when transmitting and receiving data. During data transfer, data are shifted from/to the
DATA register and to/from the bus. This implies that the DATA register cannot be accessed during byte transfers, and
Bit
765
4321
0
+0x04
BAUD[7:0]
Read/Write
R/W
Initial Value
000
0000
0
f
TWI
f
sys
2(5
BAUD
)
+
---------------------------------------[Hz]
=
BAUD
f
sys
2f
TWI
--------------
5
鈥�
=
Bit
76543210
+0x05
ADDR[7:0]
Read/Write
R/W
Initial Value
00000000
Bit
76543210
+0x06
DATA[7:0]
Read/Write
R/W
Initial Value
00000000
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