
89
XMEGA A [MANUAL]
8077I–AVR–11/2012
7.9.3
LOCK – Lock register
Bit 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
Bit 0 – LOCK: Clock System Lock
When this bit is written to one, the CTRL and PSCTRL registers cannot be changed, and the system clock selection and
prescaler settings are protected against all further updates until after the next reset. This bit is protected by the
The LOCK bit can be cleared only by a reset.
7.9.4
RTCCTRL – RTC Control register
Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
Bit 3:1 – RTCSRC[2:0]: RTC Clock Source
Table 7-4.
RTC clock source selection.
Bit 0 – RTCEN: RTC Clock Source Enable
Setting the RTCEN bit enables the selected RTC clock source for the real-time counter.
Bit
7
6543
210
+0x02
–
–LOCK
Read/Write
R
RRRR
RR
R/W
Initial Value
0
Bit
7
65
4
3
2
10
+0x03
–
RTCSRC[2:0]
RTCEN
Read/Write
R
R/W
Initial Value
0
RTCSRC[2:0]
Group Configuration
Description
000
ULP
1kHz from 32kHz internal ULP oscillator
001
TOSC
1.024kHz from 32.768kHz crystal oscillator on TOSC
010
RCOSC
1.024kHz from 32.768kHz internal oscillator
011
—
Reserved
100
—
Reserved
101
TOSC32
32.768kHz from 32.768kHz crystal oscillator on TOSC
110
—
Reserved
111
—
Reserved