- 鎮ㄧ従鍦ㄧ殑浣嶇疆锛�璨疯常IC缍� > PDF鐩寗3851 > PIC18F4450-I/P (Microchip Technology)IC PIC MCU FLASH 8KX16 40DIP PDF璩囨枡涓嬭級
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| 鍨嬭櫉锛� | PIC18F4450-I/P |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋佹暩锛� | 219/241闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC PIC MCU FLASH 8KX16 40DIP |
| 鐢㈠搧鍩硅〒妯″锛� | Asynchronous Stimulus 8-bit PIC® Microcontroller Portfolio |
| 妯欐簴鍖呰锛� | 10 |
| 绯诲垪锛� | PIC® 18F |
| 鏍稿績铏曠悊鍣細 | PIC |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 48MHz |
| 閫ｉ€氭€э細 | UART/USART锛孶SB |
| 澶栧湇瑷倷锛� | 娆犲妾㈡脯/寰╀綅锛孒LVD锛孭OR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁革細 | 34 |
| 绋嬪簭瀛樺劜鍣ㄥ閲忥細 | 16KB锛�8K x 16锛� |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | 闁冨瓨 |
| RAM 瀹归噺锛� | 768 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 4.2 V ~ 5.5 V |
| 鏁告摎杞夋彌鍣細 | A/D 13x10b |
| 鎸暕鍣ㄥ瀷锛� | 鍏ч儴 |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 40-DIP锛�0.600"锛�15.24mm锛� |
| 鍖呰锛� | 绠′欢 |
| 鐢㈠搧鐩寗闋侀潰锛� | 646 (CN2011-ZH PDF) |
| 閰嶇敤锛� | DM163025-ND - PIC DEM FULL SPEED USB DEMO BRD 444-1001-ND - DEMO BOARD FOR PICMICRO MCU |
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79
XMEGA A [MANUAL]
8077I鈥揂VR鈥�11/2012
7.
System Clock and Clock Options
7.1
Features
Fast start-up time
Safe run-time clock switching
Internal oscillators:
鈥� 32MHz run-time calibrated oscillator
鈥� 2MHz run-time calibrated oscillator
鈥� 32.768kHz calibrated oscillator
鈥� 32kHz ultra low power (ULP) oscillator with 1kHz output
External clock options
鈥� 0.4MHz - 16MHz crystal oscillator
鈥� 32.768kHz crystal oscillator
鈥� External clock
PLL with 20MHz - 128MHz output frequency
鈥� Internal and external clock options and 1x to 31x multiplication
Clock prescalers with 1x to 2048x division
Fast peripheral clocks running at 2 and 4 times the CPU clock
Automatic run-time calibration of internal oscillators
External oscillator failure detection with optional non-maskable interrupt
7.2
Overview
XMEGA devices have a flexible clock system supporting a large number of clock sources. It incorporates both accurate
internal oscillators and external crystal oscillator and resonator support. A high-frequency phase locked loop (PLL) and
clock prescalers can be used to generate a wide range of clock frequencies. A calibration feature (DFLL) is available,
and can be used for automatic run-time calibration of the internal oscillators to remove frequency drift over voltage and
temperature. An oscillator failure monitor can be enabled to issue a non-maskable interrupt and switch to the internal
oscillator if the external oscillator or PLL fails.
When a reset occurs, all clock sources except the 32kHz ultra low power oscillator are disabled. After reset, the device
will always start up running from the 2MHz internal oscillator. During normal operation, the system clock source and
prescalers can be changed from software at any time.
Figure 7-1 on page 80 presents the principal clock system in the XMEGA family of devices. Not all of the clocks need to
be active at a given time. The clocks for the CPU and peripherals can be stopped using sleep modes and power
reduction registers, as described in 鈥淧ower Management and Sleep Modes鈥� on page 99.
鐩搁棞PDF璩囨枡 |
PDF鎻忚堪 |
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| PIC18F4450T-I/ML | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 16KB FL 768 RAM 34 I/O FS-USB 2.0 RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁告摎绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁告摎 RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT |
| PIC18F4450T-I/PT | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 16KB FL 768 RAM 34 I/O FS-USB 2.0 RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁告摎绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁告摎 RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT |
| PIC18F4455-BL | 鍒堕€犲晢:POWERLITE SYSTEMS 鍔熻兘鎻忚堪:PIC18F445 W/ BOOTLOADER FOR FLASHLAB 鍒堕€犲晢:POWERLITE SYSTEMS 鍔熻兘鎻忚堪:PIC18F445 W/ BOOTLOADER, FOR FLASHLAB 鍒堕€犲晢:POWERLITE SYSTEMS 鍔熻兘鎻忚堪:PIC18F445 W/ BOOTLOADER, FOR FLASHLAB; Silicon Manufacturer:Powerlite Systems; Core Architecture:PIC; Kit Contents:Board; Features:Bootloader Programming, RS232 Connector for Boot-Loading and Serial Comms ;RoHS Compliant: Yes |
| PIC18F4455-I/ML | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 24kBF 2048RM FSUSB2 RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁告摎绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁告摎 RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT |
| PIC18F4455-I/P | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 24kBF 2048RM FSUSB2 RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁告摎绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁告摎 RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT |
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