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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | PIC18F4450-I/ML |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 133/241闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC PIC MCU FLASH 8KX16 44QFN |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Asynchronous Stimulus 8-bit PIC® Microcontroller Portfolio |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 45 |
| 绯诲垪锛� | PIC® 18F |
| 鏍稿績铏曠悊鍣細 | PIC |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 48MHz |
| 閫ｉ€氭€э細 | UART/USART锛孶SB |
| 澶栧湇瑷�(sh猫)鍌欙細 | 娆犲妾㈡脯(c猫)/寰�(f霉)浣�锛孒LVD锛孭OR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 34 |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 | 16KB锛�8K x 16锛� |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 | 闁冨瓨 |
| RAM 瀹归噺锛� | 768 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 4.2 V ~ 5.5 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 13x10b |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 44-VQFN 瑁搁湶鐒婄洡 |
| 鍖呰锛� | 绠′欢 |
| 鐢�(ch菐n)鍝佺洰閷勯爜(y猫)闈細 | 646 (CN2011-ZH PDF) |
| 閰嶇敤锛� | AC164322-ND - MODULE SOCKET MPLAB PM3 28/44QFN DM163025-ND - PIC DEM FULL SPEED USB DEMO BRD 444-1001-ND - DEMO BOARD FOR PICMICRO MCU |
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218
XMEGA A [MANUAL]
8077I鈥揂VR鈥�11/2012
19.9.5 BAUD
鈥� Baud Rate register
The baud rate (BAUD) register defines the relation between the system clock and the TWI bus clock (SCL) frequency.
The frequency relation can be expressed by using the following equation:
[1]
The BAUD register must be set to a value that results in a TWI bus clock frequency (fTWI) equal or less than 100kHz or
400kHz, depending on which standard the application should comply with. The following equation [2] expresses equation
[1] solved for the BAUD value:
[2]
The BAUD register should be written only while the master is disabled.
19.9.6 ADDR
鈥� Address register
When the address (ADDR) register is written with a slave address and the R/W bit while the bus is idle, a START
condition is issued and the 7-bit slave address and the R/W bit are transmitted on the bus. If the bus is already owned
when ADDR is written, a repeated START is issued. If the previous transaction was a master read and no acknowledge
is sent yet, the acknowledge action is sent before the repeated START condition.
After completing the operation and the acknowledge bit from the slave is received, the SCL line is forced low if arbitration
was not lost. WIF is set.
If the bus state is unknown when ADDR is written, WIF is set and BUSERR is set.
All TWI master flags are automatically cleared when ADDR is written. This includes BUSERR, ARBLOST, RIF, and WIF.
The master ADDR can be read at any time without interfering with ongoing bus activity.
19.9.7 DATA
鈥� Data register
The data (DATA) register is used when transmitting and receiving data. During data transfer, data are shifted from/to the
DATA register and to/from the bus. This implies that the DATA register cannot be accessed during byte transfers, and
Bit
765
4321
0
+0x04
BAUD[7:0]
Read/Write
R/W
Initial Value
000
0000
0
f
TWI
f
sys
2(5
BAUD
)
+
---------------------------------------[Hz]
=
BAUD
f
sys
2f
TWI
--------------
5
鈥�
=
Bit
76543210
+0x05
ADDR[7:0]
Read/Write
R/W
Initial Value
00000000
Bit
76543210
+0x06
DATA[7:0]
Read/Write
R/W
Initial Value
00000000
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| PIC18F4553-I/P | IC PIC MCU FLASH 16KX16 40-DIP |
| PIC18F46J11-I/ML | IC PIC MCU FLASH 64KB 44-QFN |
| PIC18F46J50-I/PT | IC PIC MCU FLASH 64KB 44-TQFP |
| PIC18F46K20-E/P | IC PIC MCU FLASH 32KX16 40-DIP |
| PIC18F46K20-I/MV | MCU PIC 64KB FLASH 40QFN |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| PIC18F4450T-I/ML | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 16KB FL 768 RAM 34 I/O FS-USB 2.0 RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| PIC18F4450T-I/PT | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 16KB FL 768 RAM 34 I/O FS-USB 2.0 RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| PIC18F4455-BL | 鍒堕€犲晢:POWERLITE SYSTEMS 鍔熻兘鎻忚堪:PIC18F445 W/ BOOTLOADER FOR FLASHLAB 鍒堕€犲晢:POWERLITE SYSTEMS 鍔熻兘鎻忚堪:PIC18F445 W/ BOOTLOADER, FOR FLASHLAB 鍒堕€犲晢:POWERLITE SYSTEMS 鍔熻兘鎻忚堪:PIC18F445 W/ BOOTLOADER, FOR FLASHLAB; Silicon Manufacturer:Powerlite Systems; Core Architecture:PIC; Kit Contents:Board; Features:Bootloader Programming, RS232 Connector for Boot-Loading and Serial Comms ;RoHS Compliant: Yes |
| PIC18F4455-I/ML | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 24kBF 2048RM FSUSB2 RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| PIC18F4455-I/P | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 24kBF 2048RM FSUSB2 RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
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