The I2" />
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    • 參數(shù)資料
      型號: PIC18F442-I/L
      廠商: Microchip Technology
      文件頁數(shù): 105/134頁
      文件大?。?/td> 0K
      描述: IC MCU FLASH 8KX16 EE A/D 44PLCC
      產品培訓模塊: Asynchronous Stimulus
      8-bit PIC® Microcontroller Portfolio
      標準包裝: 27
      系列: PIC® 18F
      核心處理器: PIC
      芯體尺寸: 8-位
      速度: 40MHz
      連通性: I²C,SPI,UART/USART
      外圍設備: 欠壓檢測/復位,LVD,POR,PWM,WDT
      輸入/輸出數(shù): 34
      程序存儲器容量: 16KB(8K x 16)
      程序存儲器類型: 閃存
      EEPROM 大小: 256 x 8
      RAM 容量: 768 x 8
      電壓 - 電源 (Vcc/Vdd): 4.2 V ~ 5.5 V
      數(shù)據轉換器: A/D 8x10b
      振蕩器型: 外部
      工作溫度: -40°C ~ 85°C
      封裝/外殼: 44-LCC(J 形引線)
      包裝: 管件
      配用: AC164309-ND - MODULE SKT FOR PM3 44PLCC
      XLT44L2-ND - SOCKET TRAN ICE 44PLCC
      444-1001-ND - DEMO BOARD FOR PICMICRO MCU
      其它名稱: PIC18F442I/L
      PIC16C9XX
      DS30444E - page 72
      1997 Microchip Technology Inc.
      11.2.4
      MULTI-MASTER
      The I2C protocol allows a system to have more than
      one master. This is called multi-master. When two or
      more masters try to transfer data at the same time, arbi-
      tration and synchronization occur.
      11.2.4.1
      ARBITRATION
      Arbitration takes place on the SDA line, while the SCL
      line is high. The master which transmits a high when the
      other
      master
      transmits
      a
      low
      loses
      arbitration
      (Figure 11-16), and turns off its data output stage. A
      master which lost arbitration can generate clock pulses
      until the end of the data byte where it lost arbitration.
      When the master devices are addressing the same
      device, arbitration continues into the data.
      FIGURE 11-16: MULTI-MASTER
      ARBITRATION
      (TWO MASTERS)
      Masters that also incorporate the slave function, and
      have lost arbitration must immediately switch over to
      slave-receiver mode. This is because the winning mas-
      ter-transmitter may be addressing it.
      Arbitration is not allowed between:
      A repeated START condition
      A STOP condition and a data bit
      A repeated START condition and a STOP condi-
      tion
      Care needs to be taken to ensure that these conditions
      do not occur.
      transmitter 1 loses arbitration
      DATA 1 SDA
      DATA 1
      DATA 2
      SDA
      SCL
      11.2.4.2 Clock Synchronization
      Clock synchronization occurs after the devices have
      started
      arbitration. This
      is
      performed
      using
      a
      wired-AND connection to the SCL line. A high to low
      transition on the SCL line causes the concerned
      devices to start counting off their low period. Once a
      device clock has gone low, it will hold the SCL line low
      until its SCL high state is reached. The low to high tran-
      sition of this clock may not change the state of the SCL
      line, if another device clock is still within its low period.
      The SCL line is held low by the device with the longest
      low period. Devices with shorter low periods enter a
      high wait-state, until the SCL line comes high. When the
      SCL line comes high, all devices start counting off their
      high periods. The rst device to complete its high period
      will pull the SCL line low. The SCL line high time is
      determined by the device with the shortest high period,
      FIGURE 11-17: CLOCK SYNCHRONIZATION
      CLK
      1
      CLK
      2
      SCL
      wait
      state
      start counting
      HIGH period
      counter
      reset
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      PIC18F442T-E/ML 功能描述:8位微控制器 -MCU 40MHz 8KB Flash RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
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