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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | PIC18F4410-I/ML |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 172/234闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MCU FLASH 8KX16 44QFN |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Asynchronous Stimulus 8-bit PIC® Microcontroller Portfolio |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 45 |
| 绯诲垪锛� | PIC® 18F |
| 鏍稿績铏曠悊鍣細 | PIC |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 40MHz |
| 閫ｉ€氭€э細 | I²C锛孲PI锛孶ART/USART |
| 澶栧湇瑷�(sh猫)鍌欙細 | 娆犲妾㈡脯(c猫)/寰�(f霉)浣�锛孒LVD锛孭OR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 36 |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 | 16KB锛�8K x 16锛� |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 | 闁冨瓨 |
| RAM 瀹归噺锛� | 768 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 4.2 V ~ 5.5 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 13x10b |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 44-VQFN 瑁搁湶鐒婄洡 |
| 鍖呰锛� | 绠′欢 |
| 鐢�(ch菐n)鍝佺洰閷勯爜(y猫)闈細 | 642 (CN2011-ZH PDF) |
| 閰嶇敤锛� | XLT44QFN2-ND - SOCKET TRAN ICE 44QFN/40DIP AC164322-ND - MODULE SOCKET MPLAB PM3 28/44QFN 444-1001-ND - DEMO BOARD FOR PICMICRO MCU |
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PIC18F2X1X/4X1X
DS39636D-page 44
2009 Microchip Technology Inc.
REGISTER 4-1:
RCON: RESET CONTROL REGISTER
R/W-0
R/W-1(1)
U-0
R/W-1
R-1
R/W-0(2)
R/W-0
IPEN
SBOREN
鈥擱I
TO
PD
POR
BOR
bit 7
bit 0
bit 7
IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6
SBOREN: BOR Software Enable bit(1)
If BOREN1:BOREN0 = 01:
1 = BOR is enabled
0 = BOR is disabled
If BOREN1:BOREN0 = 00, 10 or 11:
Bit is disabled and read as 鈥�0鈥�.
bit 5
Unimplemented: Read as 鈥�0鈥�
bit 4
RI: RESET Instruction Flag bit
1 = The RESET instruction was not executed (set by firmware only)
0 = The RESET instruction was executed causing a device Reset (must be set in software after
a Brown-out Reset occurs)
bit 3
TO: Watchdog Time-out Flag bit
1 = Set by power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 2
PD: Power-down Detection Flag bit
1 = Set by power-up or by the CLRWDT instruction
0 = Set by execution of the SLEEP instruction
bit 1
POR: Power-on Reset Status bit(2)
1 = A Power-on Reset has not occurred (set by firmware only)
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1 = A Brown-out Reset has not occurred (set by firmware only)
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Note 1: The SBOREN bit is only available when the BOREN1:BOREN0 Configuration
bits = 01; otherwise, it is disabled and reads as 鈥�0鈥�. See Section 4.4 鈥淏rown-out
2: The actual Reset value of POR is determined by the type of device Reset. See the
notes following this register and Section 4.6 鈥淩eset State of Registers鈥� for
additional information.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as 鈥�0鈥�
-n = Value at POR
鈥�1鈥� = Bit is set
鈥�0鈥� = Bit is cleared
x = Bit is unknown
Note 1: It is recommended that the POR bit be set after a Power-on Reset has been
detected so that subsequent Power-on Resets may be detected.
2: Brown-out Reset is said to have occurred when BOR is 鈥�0鈥� and POR is 鈥�1鈥� (assuming
that POR was set to 鈥�1鈥� by software immediately after POR).
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