2010 Microchip Technology Inc.
DS39616D-page 15
PIC18F2331/2431/4331/4431
FIGURE 1-2:
PIC18F4331/4431 (40/44-PIN) BLOCK DIAGRAM
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
OSC1/CLKI
OSC2/CLKO
MCLR/VPP
VDD, VSS
PORTA
PORTB
PORTC
RA4/AN4/CAP3/QEB
RA5/AN5/LVDIN
RB0/PWM0
RB5/KBI1/PWM4/PGM
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2/FLTA
RC2/CCP1/FLTB
RC4/INT1/SDI/SDA(3)
RC5/INT2/SCK/SCL(3)
RC6/TX/CK/SS
RC7/RX/DT/SDO
Brown-out
Reset
Note
1:
RE3 is available only when MCLR is disabled.
2:
RD4 is the alternate pin for FLTA.
3:
RC3, RC4 and RC5 are alternate pins for T0CKI/T5CKI, SDI/SDA, SCK/SCL, respectively.
4:
RD5 is the alternate pin for PWM4.
EUSART
Data EE
Synchronous
Timer0
Timer1
Timer2
Serial Port
RA3/AN3/VREF+/CAP2/QEA
RA2/AN2/VREF-/CAP1/INDX
RA1/AN1
RA0/AN0
Timing
Generation
4x PLL
HS 10-Bit
ADC
RB1/PWM1
Data Latch
Data RAM
(768 bytes)
Address Latch
Address<12>
12
Bank 0, F
BSR
FSR0
FSR1
FSR2
inc/dec
logic
Decode
4
12
4
PCH
PCL
PCLATH
8
31 Level Stack
Program Counter
PRODL
PRODH
8 x 8 Multiply
W
8
BITOP
8
ALU<8>
8
Address Latch
Program Memory
Data Latch
20
21
16
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
3
ROM Latch
Timer5
PORTE
RE0/AN6
RE1/AN7
RE2/AN8
CCP1
RB2/PWM2
RB3/PWM3
T1OSI
T1OSO
PCLATU
PCU
OSC2/CLKO/RA6
Precision
Reference
Band Gap
RB4/KBI0/PWM5
RB6/KBI2/PGC
RB7/KBI3/PGD
RC3/T0CKI/T5CKI/INT0(3)
CCP2
MCLR/VPP/RE3(1)
OSC1/CLKI/RA7
Power-Managed
INTRC
OSC
AVDD, AVSS
Mode Logic
PORTD
RD0/IT0CKI/T5CKI
RD1/SDO
RD2/SDI/SDA
RD3/SCK/SCL
RD4/FLTA(2)
RD5/PWM4(4)
RD6/PWM6
RD7/PWM7
PCPWM
MFM