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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | PIC18F27J13-I/SS |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 14/71闋�(y猫) |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC PIC MCU 128KB FLASH 28SSOP |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | 8-bit PIC® Microcontroller Portfolio |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 47 |
| 绯诲垪锛� | PIC® XLP™ 18F |
| 鏍稿績铏曠悊鍣細 | PIC |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 48MHz |
| 閫ｉ€氭€э細 | I²C锛孡IN锛孲PI锛孶ART/USART |
| 澶栧湇瑷�(sh猫)鍌欙細 | 娆犲妾㈡脯(c猫)/寰�(f霉)浣嶏紝POR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 22 |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 | 128KB锛�64K x 16锛� |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 | 闁冨瓨 |
| RAM 瀹归噺锛� | 3.8K x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 2.15 V ~ 3.6 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 10x10b/12b |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 28-SSOP锛�0.209"锛�5.30mm 瀵級 |
| 鍖呰锛� | 绠′欢 |
| 閰嶇敤锛� | MA180030-ND - BOARD DEMO PIC18F47J13 FS USB MA180029-ND - BOARD DEMO PIC18F47J53 FS USB |
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2010-2012 Microchip Technology Inc.
DS41412F-page 21
PIC18(L)F2X/4XK22
20
17
VDD
P
鈥�
Positive supply for logic and I/O pins.
8, 19
5, 16
VSS
P
鈥�
Ground reference for logic and I/O pins.
TABLE 1-2:
PIC18(L)F2XK22 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
Pin
Type
Buffer
Type
Description
PDIP,
SOIC
QFN,
UQFN
Legend:
TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels;
I = Input; O = Output; P = Power.
Note
1:
Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and
CCP2MX are set.
2:
Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and
CCP2MX are clear.
TABLE 1-3:
PIC18(L)F4XK22 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
Pin
Type
Buffer
Type
Description
PDIP
TQFP
QFN
UQFN
219
19
17
RA0/C12IN0-/AN0
RA0
I/O
TTL
Digital I/O.
C12IN0-
I
Analog Comparators C1 and C2 inverting input.
AN0
I
Analog Analog input 0.
320
20
18
RA1/C12IN1-/AN1
RA1
I/O
TTL
Digital I/O.
C12IN1-
I
Analog Comparators C1 and C2 inverting input.
AN1
I
Analog Analog input 1.
421
21
19
RA2/C2IN+/AN2/DACOUT/VREF-
RA2
I/O
TTL
Digital I/O.
C2IN+
I
Analog Comparator C2 non-inverting input.
AN2
I
Analog Analog input 2.
DACOUT
O
Analog DAC Reference output.
VREF-
I
Analog A/D reference voltage (low) input.
522
22
20
RA3/C1IN+/AN3/VREF+
RA3
I/O
TTL
Digital I/O.
C1IN+
I
Analog Comparator C1 non-inverting input.
AN3
I
Analog Analog input 3.
VREF+
I
Analog A/D reference voltage (high) input.
623
23
21
RA4/C1OUT/SRQ/T0CKI
RA4
I/O
ST
Digital I/O.
C1OUT
O
CMOS
Comparator C1 output.
SRQ
O
TTL
SR latch Q output.
T0CKI
I
ST
Timer0 external clock input.
Legend:
TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels;
I = Input; O = Output; P = Power.
Note
1:
Default pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX
and CCP2MX are set.
2:
Alternate pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX,
CCP3MX and CCP2MX are clear.
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