
2010-2012 Microchip Technology Inc.
DS39977F-page 163
PIC18F66K80 FAMILY
REGISTER 10-15: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
R/W-1
U-0
R/W-1
OSCFIP
—
BCLIP
HLVDIP
TMR3IP
TMR3GIP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
OSCFIP:
Oscillator Fail Interrupt Priority bit
1
=High priority
0
= Low priority
bit 6-4
Unimplemented:
Read as ‘0’
bit 3
BCLIP:
Bus Collision Interrupt Priority bit
1
=High priority
0
= Low priority
bit 2
HLVDIP:
High/Low-Voltage Detect Interrupt Priority bit
1
=High priority
0
= Low priority
bit 1
TMR3IP:
TMR3 Overflow Interrupt Priority bit
1
=High priority
0
= Low priority
bit 0
TMR3GIP:
TMR3 Gate Interrupt Priority bit
1
=High priority
0
= Low priority