
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 289
PIC18C601/801
FIGURE 22-19:
MASTER SSP I2C BUS START/STOP BITS TIMING WAVEFORMS
TABLE 22-18: MASTER SSP I2C BUS START/STOP BITS REQUIREMENTS
FIGURE 22-20:
MASTER SSP I2C BUS DATA TIMING
91
93
SCL
SDA
START
Condition
STOP
Condition
90
92
Param.
No.
Symbol
Characteristic
Min
Max
Units
Conditions
90
TSU:STA
START condition
100 kHz mode
2(TOSC)(BRG + 1)
—
ns
Only relevant for
Repeated START
condition
Setup time
400 kHz mode
2(TOSC)(BRG + 1)
—
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
91
THD:STA START condition
100 kHz mode
2(TOSC)(BRG + 1)
—
ns
After this period, the first
clock pulse is generated
Hold time
400 kHz mode
2(TOSC)(BRG + 1)
—
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
92
TSU:STO
STOP condition
100 kHz mode
2(TOSC)(BRG + 1)
—
ns
Setup time
400 kHz mode
2(TOSC)(BRG + 1)
—
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
93
THD:STO STOP condition
100 kHz mode
2(TOSC)(BRG + 1)
—
ns
Hold time
400 kHz mode
2(TOSC)(BRG + 1)
—
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
Note 1: Maximum pin capacitance = 10 pF for all I2C pins.
90
91
92
100
101
103
106
107
109
110
102
SCL
SDA
In
SDA
Out