PIC18F66K80 FAMILY
DS39977F-page 318
2010-2012 Microchip Technology Inc.
21.4.7
BAUD RATE
In I2C Master mode, the Baud Rate Generator (BRG)
reload value is placed in the 8 bits of the SSPADD reg-
the Baud Rate Generator will automatically begin
counting. The BRG counts down to 0 and stops until
another reload has taken place. The BRG count is
decremented twice per instruction cycle (TCY) on the
Q2 and Q4 clocks. In I2C Master mode, the BRG is
reloaded automatically.
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
instruction cycles and the BRG value loaded into
SSPADD. The SSPADD BRG value of 00h is not
supported.
FIGURE 21-19:
BAUD RATE GENERATOR BLOCK DIAGRAM
TABLE 21-3:
I2C CLOCK RATE w/BRG
FOSC
FCY
FCY * 2
BRG Value
FSCL
(2 Rollovers of BRG)
40 MHz
10 MHz
20 MHz
18h
40 MHz
10 MHz
20 MHz
1Fh
312.5 kHz
40 MHz
10 MHz
20 MHz
63h
100 kHz
16 MHz
4 MHz
8 MHz
09h
16 MHz
4 MHz
8 MHz
0Ch
308 kHz
16 MHz
4 MHz
8 MHz
27h
100 kHz
4 MHz
1 MHz
2 MHz
02h
4 MHz
1 MHz
2 MHz
09h
100 kHz
4 MHz
8 MHz
03h
Note 1:
The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
2:
A minimum 16-MHz FOSC is required for 1 MHz I2C.
SSPM<3:0>
BRG Down Counter
CLKO
FOSC/4
SSPADD<6:0>
SSPM<3:0>
SCL
Reload
Control
Reload