In I2
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� PIC18F25K80-I/SS
寤犲晢锛� Microchip Technology
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 244/351闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� MCU PIC 32KB FLASH 28SSOP
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� 8-bit PIC® Microcontroller Portfolio
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 47
绯诲垪锛� PIC® XLP™ 18F
鏍稿績铏曠悊鍣細 PIC
鑺珨灏哄锛� 8-浣�
閫熷害锛� 64MHz
閫ｉ€氭€э細 ECAN锛孖²C锛孡IN锛孲PI锛孶ART/USART
澶栧湇瑷�(sh猫)鍌欙細 娆犲妾㈡脯(c猫)/寰�(f霉)浣嶏紝LVD锛孭OR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 24
绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 32KB锛�16K x 16锛�
绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 闁冨瓨
EEPROM 澶�?銆�?/td> 1K x 8
RAM 瀹归噺锛� 3.6K x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 1.8 V ~ 5.5 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 8x12b
鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 28-SSOP锛�0.209"锛�5.30mm 瀵級
鍖呰锛� 绠′欢
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PIC18F66K80 FAMILY
DS39977F-page 318
2010-2012 Microchip Technology Inc.
21.4.7
BAUD RATE
In I2C Master mode, the Baud Rate Generator (BRG)
reload value is placed in the 8 bits of the SSPADD reg-
ister (Figure 21-19). When a write occurs to SSPBUF,
the Baud Rate Generator will automatically begin
counting. The BRG counts down to 0 and stops until
another reload has taken place. The BRG count is
decremented twice per instruction cycle (TCY) on the
Q2 and Q4 clocks. In I2C Master mode, the BRG is
reloaded automatically.
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
Table 21-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD. The SSPADD BRG value of 00h is not
supported.
FIGURE 21-19:
BAUD RATE GENERATOR BLOCK DIAGRAM
TABLE 21-3:
I2C CLOCK RATE w/BRG
FOSC
FCY
FCY * 2
BRG Value
FSCL
(2 Rollovers of BRG)
40 MHz
10 MHz
20 MHz
18h
400 kHz(1)
40 MHz
10 MHz
20 MHz
1Fh
312.5 kHz
40 MHz
10 MHz
20 MHz
63h
100 kHz
16 MHz
4 MHz
8 MHz
09h
400 kHz(1)
16 MHz
4 MHz
8 MHz
0Ch
308 kHz
16 MHz
4 MHz
8 MHz
27h
100 kHz
4 MHz
1 MHz
2 MHz
02h
333 kHz(1)
4 MHz
1 MHz
2 MHz
09h
100 kHz
16 MHz(2)
4 MHz
8 MHz
03h
1 MHz(1)
Note 1:
The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
2:
A minimum 16-MHz FOSC is required for 1 MHz I2C.
SSPM<3:0>
BRG Down Counter
CLKO
FOSC/4
SSPADD<6:0>
SSPM<3:0>
SCL
Reload
Control
Reload
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PIC18F25K80T-I/SO 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 32KB FL 4KBRM 16MIPS 12bit ADC CTMU RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
PIC18F25K80T-I/SS 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 32KB FL 4KBRM 16MIPS 12bit ADC CTMU RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
PIC18F2610-E/SO 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 64KB 3968 RAM 25 I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
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*鍨嬭櫉(h脿o) *鏁�(sh霉)閲� 寤犲晢 鎵硅櫉(h脿o) 灏佽
娣诲姞鏇村閲囪臣(g貌u)

鎴戠殑鑱�(li谩n)绯绘柟寮�

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    • 閲囪喘
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    • 浼氬憳