- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨�(m菐i)璩�(m脿i)IC缍�(w菐ng) > PDF鐩寗3864 > PIC18F25J50-I/ML (Microchip Technology)IC PIC MCU FLASH 32K 2V 28-QFN PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | PIC18F25J50-I/ML |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 24/32闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC PIC MCU FLASH 32K 2V 28-QFN |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | XLP Deep Sleep Mode PIC18 J Series MCU Overview 8-bit PIC® Microcontroller Portfolio |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 61 |
| 绯诲垪锛� | PIC® XLP™ 18F |
| 鏍稿績铏曠悊鍣細 | PIC |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 48MHz |
| 閫ｉ€氭€э細 | I²C锛孲PI锛孶ART/USART锛孶SB |
| 澶栧湇瑷�(sh猫)鍌欙細 | 娆犲妾㈡脯(c猫)/寰�(f霉)浣�锛孌MA锛孭OR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 16 |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 | 32KB锛�16K x 16锛� |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄩ(l猫i)鍨嬶細 | 闁冨瓨 |
| RAM 瀹归噺锛� | 3.8K x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 2.15 V ~ 3.6 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 10x10b |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 28-VQFN 瑁搁湶鐒婄洡(p谩n) |
| 鍖呰锛� | 绠′欢 |
| 鐢�(ch菐n)鍝佺洰閷勯爜(y猫)闈細 | 657 (CN2011-ZH PDF) |
| 閰嶇敤锛� | AC164322-ND - MODULE SOCKET MPLAB PM3 28/44QFN |
绗�1闋�(y猫)绗�2闋�(y猫)绗�3闋�(y猫)绗�4闋�(y猫)绗�5闋�(y猫)绗�6闋�(y猫)绗�7闋�(y猫)绗�8闋�(y猫)绗�9闋�(y猫)绗�10闋�(y猫)绗�11闋�(y猫)绗�12闋�(y猫)绗�13闋�(y猫)绗�14闋�(y猫)绗�15闋�(y猫)绗�16闋�(y猫)绗�17闋�(y猫)绗�18闋�(y猫)绗�19闋�(y猫)绗�20闋�(y猫)绗�21闋�(y猫)绗�22闋�(y猫)绗�23闋�(y猫)鐣�(d膩ng)鍓嶇24闋�(y猫)绗�25闋�(y猫)绗�26闋�(y猫)绗�27闋�(y猫)绗�28闋�(y猫)绗�29闋�(y猫)绗�30闋�(y猫)绗�31闋�(y猫)绗�32闋�(y猫)
PIC18F2XJXX/4XJXX FAMILY
DS39687E-page 30
2009 Microchip Technology Inc.
P1
TR
MCLR Rise Time to Enter Program/Verify
mode
鈥�1.0
渭s
P2
TPGC
Serial Clock (PGC) Period
100
鈥�
ns
P2A
TPGCL
Serial Clock (PGC) Low Time
50
鈥�
ns
P2B
TPGCH
Serial Clock (PGC) High Time
50
鈥�
ns
P3
TSET1
Input Data Setup Time to Serial Clock
鈫�
20
鈥�
ns
P4
THLD1
Input Data Hold Time from PGC
鈫�
20
鈥�
ns
P5
TDLY1
Delay Between 4-Bit Command and
Command Operand
50
鈥�
ns
P5A
TDLY1A
Delay Between 4-Bit Command Operand and
Next 4-Bit Command
50
鈥�
ns
P6
TDLY2
Delay Between Last PGC
鈫� of Command Byte
to First PGC
鈫� of Read of Data Word
20
鈥�
ns
P9
TDLY5
Delay to allow Block Programming to Occur
3.4
鈥�
ms
PIC18F2XJ10/PIC18F4XJ10
1.2
鈥�
ms
PIC18F2XJ11/PIC18F4XJ11/
PIC18F2XJ13/PIC18F4XJ13/
PIC18F2XJ5X/PIC18F4XJ5X
P10
TDLY6
Delay to allow Row Erase to Occur
49
鈥�
ms
PIC18F2XJ10/PIC18F4XJ10/
PIC18F2XJ13/PIC18F4XJ13/
PIC18F2XJ53/PIC18F4XJ53
54
鈥�
ms
PIC18F2XJ11/PIC18F4XJ11/
PIC18F2XJ50/PIC18F4XJ50
P11
TDLY7
Delay to allow Bulk Erase to Occur
475
鈥�
ms
PIC18F2XJ10/PIC18F4XJ10/
PIC18F2XJ13/PIC18F4XJ13/
PIC18F2XJ53/PIC18F4XJ53
524
鈥�
ms
PIC18F2XJ11/PIC18F4XJ11/
PIC18F2XJ50/PIC18F4XJ50
P12
THLD2
Input Data Hold Time from MCLR
鈫�
400
鈥�
渭s
P13
TSET2VDD
鈫� Setup Time to MCLR 鈫�
100
鈥�
ns
P14
TVALID
Data Out Valid from PGC
鈫�
25
鈥�
ns
P16
TDLY8
Delay Between Last PGC
鈫� and MCLR 鈫�
20
鈥�
ns
P17
THLD3MCLR
鈫� to VDD 鈫�
3鈥�
渭s
P19
TKEY1
Delay from First MCLR
鈫� to First PGC 鈫� for
Key Sequence on PGD
4鈥�
ms
P20
TKEY2
Delay from Last PGC
鈫� for Key Sequence on
PGD to Second MCLR
鈫�
50
鈥�
ns
6.0
AC/DC CHARACTERISTICS TIMING REQUIREMENTS
FOR PROGRAM/VERIFY TEST MODE (CONTINUED)
Standard Operating Conditions
Operating Temperature: 25
掳C is recommended
Param
No.
Symbol
Characteristic
Min
Max
Units
Conditions
Note 1:
External power must be supplied to the VDDCORE/VCAP pin if the on-chip voltage regulator is disabled. See
Section 2.1.1 鈥淧IC18F2XJXX/4XJXX/ LF2XJXX/LF4XJXX Devices and the On-Chip Voltage Regulator鈥� for
more information.
2:
VDD must also be supplied to the AVDD pins during programming. AVDD and AVSS should always be within 卤0.3V
of VDD and VSS, respectively.
鐩搁棞(gu膩n)PDF璩囨枡 |
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| PIC18F25J50T-I/ML | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU Full Spd USB 32KB Flsh 4KBRAM nanoWatt RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| PIC18F25J50T-I/SO | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU Full Spd USB 32KB Flsh 4KBRAM nanoWatt RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| PIC18F25J50T-I/SS | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU Full Spd USB 32KB Flsh 4KBRAM nanoWatt RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| PIC18F25K20-E/ML | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 32KB Flash 1536B RAM 25 I/O 8B RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| PIC18F25K20-E/SO | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 32KB Flash 1536B RAM 25 I/O 8B RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
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