參數(shù)資料
        型號(hào): PIC18F258-I/SO
        廠商: Microchip Technology
        文件頁(yè)數(shù): 112/116頁(yè)
        文件大?。?/td> 0K
        描述: IC MCU FLASH 16KX16 CAN 28SOIC
        產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
        8-bit PIC® Microcontroller Portfolio
        標(biāo)準(zhǔn)包裝: 27
        系列: PIC® 18F
        核心處理器: PIC
        芯體尺寸: 8-位
        速度: 40MHz
        連通性: CAN,I²C,SPI,UART/USART
        外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,LVD,POR,PWM,WDT
        輸入/輸出數(shù): 22
        程序存儲(chǔ)器容量: 32KB(16K x 16)
        程序存儲(chǔ)器類(lèi)型: 閃存
        EEPROM 大?。?/td> 256 x 8
        RAM 容量: 1.5K x 8
        電壓 - 電源 (Vcc/Vdd): 4.2 V ~ 5.5 V
        數(shù)據(jù)轉(zhuǎn)換器: A/D 5x10b
        振蕩器型: 外部
        工作溫度: -40°C ~ 85°C
        封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
        包裝: 管件
        配用: XLT28SO-1-ND - SOCKET TRANSITION 28SOIC 300MIL
        其它名稱(chēng): PIC18F258I/SO
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        2006 Microchip Technology Inc.
        DS41159E-page 93
        PIC18FXX8
        9.0
        I/O PORTS
        Depending on the device selected, there are up to five
        general purpose I/O ports available on PIC18FXX8
        devices. Some pins of the I/O ports are multiplexed
        with an alternate function from the peripheral features
        on the device. In general, when a peripheral is enabled,
        that pin may not be used as a general purpose I/O pin.
        Each port has three registers for its operation:
        TRIS register (Data Direction register)
        PORT register (reads the levels on the pins of the
        device)
        LAT register (output latch)
        The data latch (LAT register) is useful for read-modify-
        write operations on the value that the I/O pins are
        driving.
        9.1
        PORTA, TRISA and LATA
        Registers
        PORTA is a 7-bit wide, bidirectional port. The corre-
        sponding Data Direction register is TRISA. Setting a
        TRISA bit (= 1) will make the corresponding PORTA pin
        an input (i.e., put the corresponding output driver in a
        high-impedance mode). Clearing a TRISA bit (= 0) will
        make the corresponding PORTA pin an output (i.e., put
        the contents of the output latch on the selected pin). On
        a Power-on Reset, these pins are configured as inputs
        and read as ‘0’.
        Reading the PORTA register reads the status of the
        pins, whereas writing to it will write to the port latch.
        Read-modify-write operations on the LATA register
        read and write the latched output value for PORTA.
        The RA4 pin is multiplexed with the Timer0 module
        clock input to become the RA4/T0CKI pin. The RA4/
        T0CKI pin is a Schmitt Trigger input and an open-drain
        output. All other RA port pins have TTL input levels and
        full CMOS output drivers.
        The other PORTA pins are multiplexed with analog
        inputs and the analog VREF+ and VREF- inputs. The
        operation of each pin is selected by clearing/setting the
        control bits in the ADCON1 register (A/D Control
        Register 1). On a Power-on Reset, these pins are
        configured as analog inputs and read as ‘0’.
        The TRISA register controls the direction of the RA
        pins, even when they are being used as analog inputs.
        The user must ensure the bits in the TRISA register are
        maintained set, when using them as analog inputs.
        EXAMPLE 9-1:
        INITIALIZING PORTA
        Note:
        On a Power-on Reset, RA5 and RA3:RA0
        are configured as analog inputs and read
        as ‘0’. RA6 and RA4 are configured as
        digital inputs.
        CLRF
        PORTA
        ; Initialize PORTA by
        ; clearing output data latches
        CLRF
        LATA
        ; Alternate method to clear
        ; output data latches
        MOVLW
        07h
        ; Configure A/D
        MOVWF
        ADCON1 ; for digital inputs
        MOVLW
        0CFh
        ; Value used to initialize
        ; data direction
        MOVWF
        TRISA
        ; Set RA3:RA0 as inputs,
        ; RA5:RA4 as outputs
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