參數(shù)資料
型號: PIC18F2221-I/SP
廠商: Microchip Technology
文件頁數(shù): 85/110頁
文件大小: 0K
描述: IC PIC MCU FLASH 2KX16 28DIP
產(chǎn)品培訓模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標準包裝: 15
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,SPI,UART/USART
外圍設備: 欠壓檢測/復位,HLVD,POR,PWM,WDT
輸入/輸出數(shù): 25
程序存儲器容量: 4KB(2K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 4.2 V ~ 5.5 V
數(shù)據(jù)轉換器: A/D 10x10b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-DIP(0.300",7.62mm)
包裝: 管件
產(chǎn)品目錄頁面: 641 (CN2011-ZH PDF)
配用: DVA18XP280-ND - DEVICE ADAPTER 18F2220 PDIP 28LD
PIC18F2221/2321/4221/4321 FAMILY
DS39689F-page 76
2009 Microchip Technology Inc.
FIGURE 6-8:
COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND
BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)
EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)
When ‘a(chǎn)’ = 0 and ‘f’ ≥ 60h:
The instruction executes in
Direct Forced mode. ‘f’ is inter-
preted as a location in the
Access RAM between 060h
and 0FFh. This is the same as
locations
060h
to
07Fh
(Bank 0) and F80h to FFFh
(Bank 15) of data memory.
Locations below 60h are not
available in this addressing
mode.
When ‘a(chǎn)’ = 0 and ‘f’ ≤ 5Fh:
The instruction executes in
Indexed Literal Offset mode. ‘f’
is interpreted as an offset to the
address value in FSR2. The
two are added together to
obtain the address of the target
register for the instruction. The
address can be anywhere in
the data memory space.
Note that in this mode, the
correct syntax is now:
ADDWF [k], d
where ‘k’ is the same as ‘f’.
When ‘a(chǎn)’ = 1 (all values of ‘f’):
The instruction executes in
Direct mode (also known as
Direct Long mode). ‘f’ is inter-
preted as a location in one of
the 16 banks of the data
memory space. The bank is
designated by the Bank Select
Register (BSR). The address
can be in any implemented
bank in the data memory
space.
000h
060h
100h
F00h
F80h
FFFh
Valid range
00h
60h
80h
FFh
Data Memory
Access RAM
Bank 0
Bank 1
through
Bank 14
Bank 15
SFRs
000h
080h
100h
F00h
F80h
FFFh
Data Memory
Bank 0
Bank 1
through
Bank 14
Bank 15
SFRs
FSR2H
FSR2L
ffffffff
001001da
ffffffff
001001da
000h
080h
100h
F00h
F80h
FFFh
Data Memory
Bank 0
Bank 1
through
Bank 14
Bank 15
SFRs
for ‘f’
BSR
00000000
080h
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