PIC18F1230/1330
2009 Microchip Technology Inc.
DS39758D-page 171
REGISTER 16-3:
ADCON2: A/D CONTROL REGISTER 2
R/W-0
U-0
R/W-0
ADFM
—
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
ADFM:
A/D Result Format Select bit
1
= Right justified
0
= Left justified
bit 6
Unimplemented:
Read as ‘0’
bit 5-3
ACQT2:ACQT0:
A/D Acquisition Time Select bits
111
= 20 TAD
110
= 16 TAD
101
= 12 TAD
100
= 8 TAD
011
= 6 TAD
010
= 4 TAD
001
= 2 TAD
000
= 0 TAD(1)
bit 2-0
ADCS2:ADCS0:
A/D Conversion Clock Select bits
111
= FRC (clock derived from A/D RC oscillator)(1)
110
= FOSC/64
101
= FOSC/16
100
= FOSC/4
011
= FRC (clock derived from A/D RC oscillator)(1)
010
= FOSC/32
001
= FOSC/8
000
= FOSC/2
Note 1:
If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D
clock starts. This allows the SLEEP instruction to be executed before starting a conversion.
