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| 鍨嬭櫉锛� | PIC18C858-I/L |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋佹暩(sh霉)锛� | 54/246闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC PIC MCU OTP 16KX16 84PLCC |
| 鐢�(ch菐n)鍝佸煿瑷撴ā濉婏細 | Asynchronous Stimulus 8-bit PIC® Microcontroller Portfolio |
| 妯欐簴鍖呰锛� | 16 |
| 绯诲垪锛� | PIC® 18C |
| 鏍稿績铏曠悊鍣細 | PIC |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 40MHz |
| 閫ｉ€氭€э細 | CAN锛孖²C锛孲PI锛孶ART/USART |
| 澶栧湇瑷倷锛� | 娆犲妾㈡脯/寰╀綅锛孡VD锛孭OR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 68 |
| 绋嬪簭瀛樺劜鍣ㄥ閲忥細 | 32KB锛�16K x 16锛� |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | OTP |
| RAM 瀹归噺锛� | 1.5K x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 4.2 V ~ 5.5 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 16x10b |
| 鎸暕鍣ㄥ瀷锛� | 澶栭儴 |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 84-LCC锛圝 褰㈠紩绶氾級 |
| 鍖呰锛� | 绠′欢 |
| 閰嶇敤锛� | AC164310-ND - MODULE SKT FOR PM3 84PLCC DVA18XL840-ND - ADAPTER DEVICE ICE 84PLCC AC174012-ND - MODULE SKT PROMATEII 84PLCC |
| 鍏跺畠鍚嶇ū锛� | PIC18C858I/L |
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2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 147
PIC18CXX8
15.4
MSSP I2C Operation
The MSSP module in I2C mode, fully implements all
master and slave functions (including general call sup-
port) and provides interrupts on START and STOP bits
in hardware to determine a free bus (Multi-master
mode). The MSSP module implements the standard
mode specifications, as well as 7-bit and 10-bit
addressing.
Two pins are used for data transfer. These are the
RC3/SCK/SCL pin, which is the clock (SCL), and the
RC4/SDI/SDA pin, which is the data (SDA). The user
must configure these pins as inputs or outputs through
the TRISC<4:3> bits.
The MSSP module functions are enabled by setting
MSSP Enable bit SSPEN (SSPCON1 register).
FIGURE 15-6: MSSP BLOCK DIAGRAM
(I2C MODE)
The MSSP module has these six registers for I2C oper-
ation:
MSSP Control Register1 (SSPCON1)
MSSP Control Register2 (SSPCON2)
MSSP Status Register (SSPSTAT)
Serial Receive/Transmit Buffer (SSPBUF)
MSSP Shift Register (SSPSR) - Not directly
accessible
MSSP Address Register (SSPADD)
The SSPCON1 register allows control of the I2C oper-
ation.
The
SSPM3:SSPM0
mode
selection
bits
(SSPCON1 register) allow one of the following I2C
modes to be selected:
I2C Master mode, clock = OSC/4 (SSPADD +1)
I2C Slave mode (7-bit address)
I2C Slave mode (10-bit address)
I2C Slave mode (7-bit address), with START and
STOP bit interrupts enabled
I2C Slave mode (10-bit address), with START and
STOP bit interrupts enabled
I2C Firmware controlled master operation, slave
is idle
Selection of any I2C mode with the SSPEN bit set,
forces the SCL and SDA pins to be open drain, pro-
vided these pins are programmed to inputs by setting
the appropriate TRISC bits.
15.4.1
SLAVE MODE
In Slave mode, the SCL and SDA pins must be config-
ured as inputs (TRISC<4:3> set). The MSSP module
will override the input state with the output data when
required (slave-transmitter).
When an address is matched, or the data transfer after
an address match is received, the hardware automati-
cally will generate the acknowledge (ACK) pulse and
load the SSPBUF register with the received value cur-
rently in the SSPSR register.
If either or both of the following conditions are true, the
MSSP module will not give this ACK pulse:
a)
The buffer full bit BF (SSPCON1 register) was
set before the transfer was received.
b)
The overflow bit SSPOV (SSPCON1 register)
was set before the transfer was received.
In this event, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR registers) is set.
The BF bit is cleared by reading the SSPBUF register,
while bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specification, as well as the requirement of the
MSSP module, is shown in timing parameter #100 and
parameter #101.
Read
Write
SSPSR reg
Match Detect
SSPADD reg
START and
STOP bit detect
SSPBUF reg
Internal
Data Bus
Addr Match
Set, RESET
S, P bits
(SSPSTAT reg)
RC3/SCK/SCL
RC4/
Shift
Clock
MSb
SDI/
LSb
SDA
Note:
I/O pins have diode protection to VDD and VSS.
鐩搁棞PDF璩囨枡 |
PDF鎻忚堪 |
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