
PIC18CXX2
DS39026C-page 22
2001 Microchip Technology Inc.
If the main oscillator is configured for HS-PLL mode, an
oscillator start-up time (TOST) plus an additional PLL
time-out (TPLL) will occur. The PLL time-out is typically
2 ms and allows the PLL to lock to the main oscillator
frequency. A timing diagram, indicating the transition
from the Timer1 oscillator to the main oscillator for
FIGURE 2-10:
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS WITH PLL)
If the main oscillator is configured in the RC, RCIO, EC
or ECIO modes, there is no oscillator start-up time-out.
Operation will resume after eight cycles of the main
oscillator have been counted. A timing diagram, indi-
cating the transition from the Timer1 oscillator to the
main oscillator for RC, RCIO, EC and ECIO modes, is
FIGURE 2-11:
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC)
Q4
Q1
Q2 Q3
Q4
Q1 Q2
OSC1
Internal System
SCS
(OSCCON<0>)
Program Counter
PC
PC + 2
Note 1: TOST = 1024TOSC (drawing not to scale).
T1OSI
Clock
TOST
Q3
PC + 4
TPLL
TOSC
TT1P
TSCS
Q4
OSC2
PLL Clock
Input
1
2
3
4
56
78
Q3
Q4
Q1
Q1 Q2
Q3
Q4 Q1
Q2
Q3
OSC1
Internal System
SCS
(OSCCON<0>)
Program Counter
PC
PC + 2
Note 1: RC oscillator mode assumed.
PC + 4
T1OSI
Clock
OSC2
Q4
TT1P
TOSC
TSCS
1
23
45
6
78