參數(shù)資料
型號: PIC17LC766T-08/PT
廠商: Microchip Technology
文件頁數(shù): 93/159頁
文件大?。?/td> 0K
描述: IC MCU OTP 16KX16 A/D PWM 80TQFP
標(biāo)準(zhǔn)包裝: 1,200
系列: PIC® 17C
核心處理器: PIC
芯體尺寸: 8-位
速度: 8MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 66
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: OTP
RAM 容量: 902 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x10b
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 80-TQFP
包裝: 帶卷 (TR)
PIC17C7XX
DS30289B-page 38
2000 Microchip Technology Inc.
REGISTER 6-5:
PIR2 REGISTER (ADDRESS: 10h, BANK 4)
R/W-0
U-0
R/W-0
R-1
R-0
SSPIF
BCLIF
ADIF
CA4IF
CA3IF
TX2IF
RC2IF
bit 7
bit 0
bit 7
SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit
1
= The SSP interrupt condition has occurred and must be cleared in software before returning
from the Interrupt Service Routine. The conditions that will set this bit are:
SPI:
A transmission/reception has taken place.
I2C Slave/Master:
A transmission/reception has taken place.
I2C Master:
The initiated START condition was completed by the SSP module.
The initiated STOP condition was completed by the SSP module.
The initiated Restart condition was completed by the SSP module.
The initiated Acknowledge condition was completed by the SSP module.
A START condition occurred while the SSP module was idle (Multi-master system).
A STOP condition occurred while the SSP module was idle (Multi-master system).
0
= An SSP interrupt condition has NOT occurred
bit 6
BCLIF: Bus Collision Interrupt Flag bit
1
= A bus collision has occurred in the SSP, when configured for I2C Master mode
0
= No bus collision has occurred
bit 5
ADIF: A/D Module Interrupt Flag bit
1
= An A/D conversion is complete
0
= An A/D conversion is not complete
bit 4
Unimplemented: Read as ’0’
bit 3
CA4IF: Capture4 Interrupt Flag bit
1
= Capture event occurred on RE3/CAP4 pin
0
= Capture event did not occur on RE3/CAP4 pin
bit 2
CA3IF: Capture3 Interrupt Flag bit
1
= Capture event occurred on RG4/CAP3 pin
0
= Capture event did not occur on RG4/CAP3 pin
bit 1
TX2IF:USART2 Transmit Interrupt Flag bit (state controlled by hardware)
1
= USART2 Transmit buffer is empty
0
= USART2 Transmit buffer is full
bit 0
RC2IF: USART2 Receive Interrupt Flag bit (state controlled by hardware)
1
= USART2 Receive buffer is full
0
= USART2 Receive buffer is empty
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR Reset
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
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