參數資料
型號: PIC17LC766T-08/L
廠商: Microchip Technology
文件頁數: 17/159頁
文件大?。?/td> 0K
描述: IC MCU OTP 16KX16 A/D PWM 84PLCC
標準包裝: 300
系列: PIC® 17C
核心處理器: PIC
芯體尺寸: 8-位
速度: 8MHz
連通性: I²C,SPI,UART/USART
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數: 66
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: OTP
RAM 容量: 902 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數據轉換器: A/D 16x10b
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 84-LCC(J 形引線)
包裝: 帶卷 (TR)
Section 4 Clock Pulse Generator (CPG)
R01UH0025EJ0300 Rev. 3.00
Page 81 of 1336
Sep 24, 2010
SH7261 Group
4.3
Clock Operating Modes
Table 4.2 shows the relationship between the combinations of the mode control pins (MD_CLK1
and MD_CLK0) and the clock operating modes. Table 4.2 shows the usable frequency ranges in
the clock operating modes.
Table 4.2
Clock Operating Modes
Pin Values
Clock I/O
Mode MD_CLK1
MD_CLK0
Source
Output
PLL Circuit 2
On/Off
PLL Circuit 1
On/Off
CKIO Frequency
0
EXTAL or
crystal resonator
CKIO
ON (
×4)
ON (
×1, 2, 3, 4) (EXTAL or crystal
resonator)
×4
2
1
0
EXTAL or
crystal resonator
CKIO
ON (
×2)
ON (
×1, 2, 3, 4,
6, 8)
(EXTAL or crystal
resonator)
×2
3
1
CKIO
OFF
ON (
×1, 2, 3, 4,
6, 8)
(CKIO)
Mode 0
The frequency of the signal received from the EXTAL pin or crystal resonator is quadrupled
by the PLL circuit 2 before it is supplied to the LSI as the clock signal. This enables to use the
external clock of lower frequency. Either a crystal resonator with a frequency in the range from
10 to 15 MHz or an external signal in the same frequency range input on the EXTAL pin may
be used. The frequency range of CKIO is from 40 to 60 MHz.
Mode 2
The frequency of the signal received from the EXTAL pin or crystal resonator is doubled by
the PLL circuit 2 before it is supplied to the LSI as the clock signal. This enables to use the
external clock of lower frequency. An external signal with a frequency in the range from 10 to
30 MHz or a crystal resonator with 10 to 20 MHz may be used. The frequency range of CKIO
is from 20 to 60 MHz.
Mode 3
In mode 3, the CKIO pin functions as an input pin and draws an external clock signal. The
PLL circuit 1 shapes its waveform and the setting of the frequency control register multiplies
its frequency before the clock enters the LSI. Frequency between 20 to 60 MHz can be input to
the CKIO pin. For reduced current and hence power consumption, pull up the EXTAL pin and
open the XTAL pin when the LSI is used in mode 3.
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