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  • 參數(shù)資料
    型號: PIC17LC766-08/L
    廠商: Microchip Technology
    文件頁數(shù): 10/159頁
    文件大小: 0K
    描述: IC MCU OTP 16KX16 A/D PWM 84PLCC
    標(biāo)準(zhǔn)包裝: 16
    系列: PIC® 17C
    核心處理器: PIC
    芯體尺寸: 8-位
    速度: 8MHz
    連通性: I²C,SPI,UART/USART
    外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
    輸入/輸出數(shù): 66
    程序存儲器容量: 32KB(16K x 16)
    程序存儲器類型: OTP
    RAM 容量: 902 x 8
    電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
    數(shù)據(jù)轉(zhuǎn)換器: A/D 16x10b
    振蕩器型: 外部
    工作溫度: 0°C ~ 70°C
    封裝/外殼: 84-LCC(J 形引線)
    包裝: 管件
    Section 3 Floating-Point Unit (FPU)
    R01UH0025EJ0300 Rev. 3.00
    Page 75 of 1336
    Sep 24, 2010
    SH7261 Group
    3.5
    FPU Exceptions
    3.5.1
    FPU Exception Sources
    FPU exceptions may occur on floating-point operation instruction and the exception sources are as
    follows:
    FPU error (E): When FPSCR.DN = 0 and a denormalized number is input (No chance to occur
    in the SH2A-FPU)
    Invalid operation (V): In case of an invalid operation, such as NaN input
    Division by zero (Z): Division with a zero divisor
    Overflow (O): When the operation result overflows
    Underflow (U): When the operation result underflows
    Inexact exception (I): When overflow, underflow, or rounding occurs
    The FPU exception cause field in FPSCR contains bits corresponding to all of above sources E, V,
    Z, O, U, and I, and the FPU exception flag and enable fields in FPSCR contain bits corresponding
    to sources V, Z, O, U, and I, but not E. Thus, FPU errors cannot be disabled.
    When an FPU exception occurs, the corresponding bit in the FPU exception cause field is set to 1,
    and 1 is added to the corresponding bit in the FPU exception flag field. When an FPU exception
    does not occur, the corresponding bit in the FPU exception cause field is cleared to 0, but the
    corresponding bit in the FPU exception flag field remains unchanged.
    3.5.2
    FPU Exception Handling
    FPU exception handling is initiated in the following cases:
    FPU error (E): FPSCR.DN = 0 and a denormalized number is input (No chance to occur in the
    SH2A-FPU)
    Invalid operation (V): FPSCR.Enable.V = 1 and invalid operation
    Division by zero (Z): FPSCR.Enable.Z = 1 and division with a zero divisor
    Overflow (O): FPSCR.Enable.O = 1 and instruction with possibility of operation result
    overflow
    Underflow (U): FPSCR.Enable.U = 1 and instruction with possibility of operation result
    underflow
    Inexact exception (I): FPSCR.Enable.I = 1 and instruction with possibility of inexact operation
    result
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