參數(shù)資料
型號： PIC17C75X
英文描述： Micropower Precision Series Reference Family; Package: SOT; No of Pins: 3; Temperature Range: 0°C to +70°C
文件頁數(shù)： 53/71頁
文件大?。?/td> 1173K
代理商： PIC17C75X
1996 Microchip Technology Inc.
DS30412C-page 57
PIC17C4X
Example 9-1 shows the instruction sequence to initial-
ize PORTB. The Bank Select Register (BSR) must be
selected to Bank 0 for the port to be initialized.
EXAMPLE 9-1:
INITIALIZING PORTB
MOVLB 0
; Select Bank 0
CLRF
PORTB
; Initialize PORTB by clearing
;
output data latches
MOVLW 0xCF
; Value used to initialize
;
data direction
MOVWF DDRB
;
Set RB<3:0> as inputs
;
RB<5:4> as outputs
;
RB<7:6> as inputs
TABLE 9-3:
PORTB FUNCTIONS
TABLE 9-4:
REGISTERS/BITS ASSOCIATED WITH PORTB
Name
Bit
Buffer Type
Function
RB0/CAP1
bit0
ST
Input/Output or the RB0/CAP1 input pin. Software programmable weak pull-
up and interrupt on change features.
RB1/CAP2
bit1
ST
Input/Output or the RB1/CAP2 input pin. Software programmable weak pull-
up and interrupt on change features.
RB2/PWM1
bit2
ST
Input/Output or the RB2/PWM1 output pin. Software programmable weak
pull-up and interrupt on change features.
RB3/PWM2
bit3
ST
Input/Output or the RB3/PWM2 output pin. Software programmable weak
pull-up and interrupt on change features.
RB4/TCLK12
bit4
ST
Input/Output or the external clock input to Timer1 and Timer2. Software pro-
grammable weak pull-up and interrupt on change features.
RB5/TCLK3
bit5
ST
Input/Output or the external clock input to Timer3. Software programmable
weak pull-up and interrupt on change features.
RB6
bit6
ST
Input/Output pin. Software programmable weak pull-up and interrupt on
change features.
RB7
bit7
ST
Input/Output pin. Software programmable weak pull-up and interrupt on
change features.
Legend: ST = Schmitt Trigger input.
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other
resets
(Note1)
12h, Bank 0
PORTB
PORTB data latch
xxxx xxxx
uuuu uuuu
11h, Bank 0
DDRB
Data direction register for PORTB
1111 1111
10h, Bank 0
PORTA
RBPU
—
RA5
RA4
RA3
RA2
RA1/T0CKI
RA0/INT
0-xx xxxx
0-uu uuuu
06h, Unbanked
CPUSTA
—
STKAV
GLINTD
TO
PD
——
--11 11--
--11 qq--
07h, Unbanked
INTSTA
PEIF
T0CKIF
T0IF
INTF
PEIE
T0CKIE
T0IE
INTE
0000 0000
16h, Bank 1
PIR
RBIF
TMR3IF
TMR2IF
TMR1IF
CA2IF
CA1IF
TXIF
RCIF
0000 0010
17h, Bank 1
PIE
RBIE
TMR3IE
TMR2IE
TMR1IE
CA2IE
CA1IE
TXIE
RCIE
0000 0000
16h, Bank 3
TCON1
CA2ED1
CA2ED0
CA1ED1
CA1ED0
T16
TMR3CS
TMR2CS
TMR1CS
0000 0000
17h, Bank 3
TCON2
CA2OVF CA1OVF
PWM2ON
PWM1ON
CA1/PR3
TMR3ON
TMR2ON
TMR1ON 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = Value depends on condition.
Shaded cells are not used by PORTB.
Note 1:
Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
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