
PIC17C4X
DS30412C-page 160
1996 Microchip Technology Inc.
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 17-9: USART MODULE: SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 17-9:
SERIAL PORT SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 17-10: USART MODULE: SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 17-10: SERIAL PORT SYNCHRONOUS RECEIVE REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ
Max
Units Conditions
120
TckH2dtV
SYNC XMIT (MASTER & SLAVE)
Clock high to data out valid
—
65
ns
121
TckRF
Clock out rise time and fall time (Master
Mode)
—10
35
ns
122
TdtRF
Data out rise time and fall time
—
10
35
ns
Data in “Typ” column is at 5V, 25
°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Parameter
No.
Sym
Characteristic
Min
Typ
Max
Units Conditions
125
TdtV2ckL
SYNC RCV (MASTER & SLAVE)
Data hold before CK
↓ (DT hold time)
15
—
ns
126
TckL2dtl
Data hold after CK
↓ (DT hold time)
15
—
ns
Data in “Typ” column is at 5V, 25
°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
121
120
122
RA5/TX/CK
RA4/RX/DT
pin
125
126
RA5/TX/CK
RA4/RX/DT
pin