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參數(shù)資料
型號： PIC16LF77T-I/PTG
廠商： Microchip Technology
文件頁數(shù)： 39/104頁
文件大?。?/td> 0K
描述： IC MCU FLASH 8KX14 44TQFP
標(biāo)準(zhǔn)包裝： 1,200
系列： PIC® 16F
核心處理器： PIC
芯體尺寸： 8-位
速度： 20MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 33
程序存儲器容量： 14KB（8K x 14）
程序存儲器類型： 閃存
RAM 容量： 368 x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x8b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-TQFP
包裝： 帶卷 (TR)
2002 Microchip Technology Inc.
DS30325B-page 29
PIC16F7X
3.0
READING PROGRAM MEMORY
The FLASH Program Memory is readable during nor-
mal operation over the entire VDD range. It is indirectly
addressed through Special Function Registers (SFR).
Up to 14-bit numbers can be stored in memory for use
as calibration parameters, serial numbers, packed 7-bit
ASCII, etc. Executing a program memory location con-
taining data that forms an invalid instruction results in a
NOP
.
There are five SFRs used to read the program and
memory. These registers are:
PMCON1
PMDATA
PMDATH
PMADR
PMADRH
The program memory allows word reads. Program
memory access allows for checksum calculation and
reading calibration tables.
When interfacing to the program memory block, the
PMDATH:PMDATA registers form a two-byte word,
which
holds
the
14-bit
data
for
reads.
The
PMADRH:PMADR registers form a two-byte word,
which holds the 13-bit address of the FLASH location
being accessed. These devices can have up to 8K
words of program FLASH, with an address range from
0h to 3FFFh. The unused upper bits in both the
PMDATH and PMADRH registers are not implemented
and read as “0’s”.
3.1
PMADR
The address registers can address up to a maximum of
8K words of program FLASH.
When selecting a program address value, the MSByte
of the address is written to the PMADRH register and
the LSByte is written to the PMADR register. The upper
MSbits of PMADRH must always be clear.
3.2
PMCON1 Register
PMCON1 is the control register for memory accesses.
The control bit RD initiates read operations. This bit
cannot be cleared, only set, in software. It is cleared in
hardware at the completion of the read operation.
REGISTER 3-1:
PMCON1 REGISTER (ADDRESS 18Ch)
R-1
U-0
U-x
U-0
R/S-0
reserved
—
RD
bit 7
bit 0
bit 7
Reserved: Read as ‘1’
bit 6-1
Unimplemented: Read as '0'
bit 0
RD: Read Control bit
1
= Initiates a FLASH read, RD is cleared in hardware. The RD bit can only be set (not cleared)
in software.
0
= FLASH read completed
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR reset
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
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