366
6062N–ATARM–3-Oct-11
AT91SAM9261
30.7.2
SPI Mode Register
Name:
SPI_MR
Addresses: 0xFFFC8004 (0), 0xFFFCC004 (1)
Access Type: Read/Write
MSTR: Master/Slave Mode
0 = SPI is in Slave mode.
1 = SPI is in Master mode.
PS: Peripheral Select
0 = Fixed Peripheral Select.
1 = Variable Peripheral Select.
PCSDEC: Chip Select Decode
0 = The chip selects are directly connected to a peripheral device.
1 = The four chip select lines are connected to a 4- to 16-bit decoder.
When PCSDEC equals one, up to 15 Chip Select signals can be generated with the four lines using an external 4- to 16-bit
decoder. The Chip Select Registers define the characteristics of the 15 chip selects according to the following rules:
SPI_CSR0 defines peripheral chip select signals 0 to 3.
SPI_CSR1 defines peripheral chip select signals 4 to 7.
SPI_CSR2 defines peripheral chip select signals 8 to 11.
SPI_CSR3 defines peripheral chip select signals 12 to 14.
MODFDIS: Mode Fault Detection
0 = Mode fault detection is enabled.
1 = Mode fault detection is disabled.
LLB: Local Loopback Enable
0 = Local loopback path disabled.
1 = Local loopback path enabled
LLB controls the local loopback on the data serializer for testing in Master Mode only. (MISO is internally connected on
MOSI.)
31
30
29
28
27
26
25
24
DLYBCS
23
22
21
20
19
18
17
16
––––
PCS
15
14
13
12
11
10
9
8
––––––––
76
543210
LLB
–
MODFDIS
–
PCSDEC
PS
MSTR