
2002 Microchip Technology Inc.
Advance Information
DS41120B-page 75
PIC16C717/770/771
9.1.7
SLEEP OPERATION
In Master mode, all module clocks are halted and the
transmission/reception will remain in that state until the
device wakes from SLEEP. After the device returns to
Normal mode, the module will continue to transmit/
receive data.
In Slave mode, the SPI transmit/receive shift register
operates asynchronously to the device. This allows the
device to be placed in SLEEP mode and data to be
shifted into the SPI transmit/receive shift register.
When all eight bits have been received, the SSPIF
interrupt flag bit will be set and if enabled will wake the
device from SLEEP.
9.1.8
EFFECTS OF A RESET
A RESET disables the MSSP module and terminates
the current transfer.
TABLE 9-1:
REGISTERS ASSOCIATED WITH SPI OPERATION
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR, BOR
MCLR, WDT
0Bh, 8Bh,
10Bh,18Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
0Ch
PIR1
—
ADIF
—
SSPIF
CCP1IF
TMR2IF
TMR1IF
-0-- 0000
8Ch
PIE1
—
ADIE
—
SSPIE
CCP1IE
TMR2IE
TMR1IE
-0-- 0000
13h
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx
uuuu uuuu
14h
SSPCON
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000
94h
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000
9Dh
ANSEL
--11 1111
86h
TRISB
1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used by the MSSP in SPI mode.