參數(shù)資料
型號(hào): PIC16LC72-04/SS
廠商: Microchip Technology
文件頁數(shù): 64/111頁
文件大小: 0K
描述: IC MCU OTP 2KX14 A/D PWM 28SSOP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 47
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 4MHz
連通性: I²C,SPI
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 22
程序存儲(chǔ)器容量: 3.5KB(2K x 14)
程序存儲(chǔ)器類型: OTP
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2.5 V ~ 6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 5x8b
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 28-SSOP(0.209",5.30mm 寬)
包裝: 管件
PIC16C72 Series
DS39016A-page 56
Preliminary
1998 Microchip Technology Inc.
9.1
A/D Acquisition Requirements
For the A/D converter to meet its specied accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 9-4. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD). The
source impedance affects the offset voltage at the ana-
log input (due to pin leakage current). The maximum
recommended impedance for analog sources is 10
k
. After the analog input channel is selected
(changed) this acquisition must be done before the
conversion can be started.
To calculate the minimum acquisition time, TACQ, see
the PICmicro Mid-Range MCU Reference Manual,
DS33023. This equation calculates the acquisition time
to within 1/2 LSb error (512 steps for the A/D). The 1/2
LSb error is the maximum error allowed for the A/D to
meet its specied accuracy.
FIGURE 9-4:
ANALOG INPUT MODEL
CPIN
VA
Rs
ANx
5 pF
VDD
VT = 0.6V
I leakage
RIC
≤ 1k
Sampling
Switch
SS
RSS
CHOLD
= DAC capacitance
VSS
6V
Sampling Switch
5V
4V
3V
2V
5 6 7 8 9 10 11
( k
)
VDD
= 51.2 pF
± 500 nA
Legend CPIN
VT
I leakage
RIC
SS
CHOLD
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
various junctions
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