Module: MSSP (I2C Master Mo" />
參數(shù)資料
型號: PIC16F884-I/P
廠商: Microchip Technology
文件頁數(shù): 14/16頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 4KX14 40DIP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 10
系列: PIC® 16F
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 35
程序存儲器容量: 7KB(4K x 14)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 14x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 40-DIP(0.600",15.24mm)
包裝: 管件
產(chǎn)品目錄頁面: 640 (CN2011-ZH PDF)
配用: DVA18XP400-ND - DEVICE ADAPTER 18F4220 PDIP 40LD
444-1001-ND - DEMO BOARD FOR PICMICRO MCU
2009 Microchip Technology Inc.
DS80302F-page 7
PIC16F88X
6.
Module: MSSP (I2C Master Mode)
When the MSSP is I2C Master mode with a
slave device stretching the clock, the clock
generation does not function as described in the
data sheet.
When a slave device is performing clock stretching
by pulling the SCL line low, the master device
should continuously sample the SCL line to
determine when all slaves have released SCL.
When SCL is released, the master device should
wait one BRG period to ensure a constant SCL
high time.
The current implementation does not ensure
accurate SCL high time. During clock stretch, the
MSSP device will erroneously continue running
the BRG counter. At the end of the clock stretch
the BRG counter continues to count down for the
remainder of the BRG period, and then the MSSP
device will immediately resume transmitting the
data.
Figure 1 illustrates an expected I2C transmission
in which the SCL line is completely controlled by
the master device and the slave device does not
attempt to stretch the clock period.
Figure 2 illustrates the expected operation of an
I2C transmission in which the slave device has
stretched the clock period by holding the SCL line
low. The high time of the SCL pulse is constant,
regardless of the duration of the clock stretch.
Figure 3 and Figure 4 illustrate an actual I2C
transmission in which the slave has stretched the
clock period by holding the SCL line low. Note that
the high time of the SCL signal has shortened from
the expected time.
FIGURE 1:
ACTUAL (CORRECT) OPERATION WITHOUT CLOCK STRETCHING
FIGURE 2:
EXPECTED OPERATION WITH CLOCK STRETCHING
BRG Period
SDA
SCL
Master
Slave
BRG Period
SDA
SCL
Master
Slave
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PIC16F886-E/SO 功能描述:8位微控制器 -MCU 14KB Flash 368 RAM 25 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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