TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO V
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2001 Microchip Technology Inc.
DS30292C-page 127
PIC16F87X
FIGURE 12-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
PIE2
873
874
876
877
-r-0 0--0
-r-u u--u
PCON
873
874
876
877
---- --qq
---- --uu
PR2
873
874
876
877
1111 1111
SSPADD
873
874
876
877
0000 0000
uuuu uuuu
SSPSTAT
873
874
876
877
--00 0000
--uu uuuu
TXSTA
873
874
876
877
0000 -010
uuuu -uuu
SPBRG
873
874
876
877
0000 0000
uuuu uuuu
ADRESL
873
874
876
877
xxxx xxxx
uuuu uuuu
ADCON1
873
874
876
877
0--- 0000
u--- uuuu
EEDATA
873
874
876
877
0--- 0000
u--- uuuu
EEADR
873
874
876
877
xxxx xxxx
uuuu uuuu
EEDATH
873
874
876
877
xxxx xxxx
uuuu uuuu
EEADRH
873
874
876
877
xxxx xxxx
uuuu uuuu
EECON1
873
874
876
877
x--- x000
u--- u000
u--- uuuu
EECON2
873
874
876
877
---- ----
TABLE 12-6:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Devices
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset
Wake-up via WDT or
Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as 鈥�0鈥�, q = value depends on condition,
r
= reserved, maintain clear
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 12-5 for RESET value for specific condition.
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
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