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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� PIC16F876A-I/ML
寤犲晢锛� Microchip Technology
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8-bit PIC® Microcontroller Portfolio
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鏍稿績铏曠悊鍣細 PIC
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RAM 瀹归噺锛� 368 x 8
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鏁�(sh霉)鎿�(j霉)杞夋彌鍣細 A/D 5x10b
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鐢㈠搧鐩寗闋侀潰锛� 641 (CN2011-ZH PDF)
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PIC16F87XA
DS39582B-page 20
2003 Microchip Technology Inc.
Bank 1
80h(3)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 31, 150
81h
OPTION_REG
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
82h(3)
PCL
Program Counter (PC) Least Significant Byte
0000 0000
83h(3)
STATUS
IRP
RP1
RP0
TO
PD
ZDC
C
0001 1xxx
84h(3)
FSR
Indirect Data Memory Address Pointer
xxxx xxxx
85h
TRISA
鈥�
PORTA Data Direction Register
--11 1111
86h
TRISB
PORTB Data Direction Register
1111 1111
87h
TRISC
PORTC Data Direction Register
1111 1111
88h(4)
TRISD
PORTD Data Direction Register
1111 1111
89h(4)
TRISE
IBF
OBF
IBOV
PSPMODE
鈥�
PORTE Data Direction bits
0000 -111
8Ah(1,3)
PCLATH
鈥�
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
8Bh(3)
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
8Ch
PIE1
PSPIE(2)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE 0000 0000 25, 151
8Dh
PIE2
鈥擟MIE
鈥�
EEIE
BCLIE
鈥�
CCP2IE
-0-0 0--0
8Eh
PCON
鈥�
鈥擯OR
BOR
---- --qq
8Fh
鈥�
Unimplemented
鈥�
90h
鈥�
Unimplemented
鈥�
91h
SSPCON2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
0000 0000
92h
PR2
Timer2 Period Register
1111 1111
93h
SSPADD
Synchronous Serial Port (I2C mode) Address Register
0000 0000
94h
SSPSTAT
SMP
CKE
D/A
PS
R/W
UA
BF
0000 0000
95h
鈥�
Unimplemented
鈥�
96h
鈥�
Unimplemented
鈥�
97h
鈥�
Unimplemented
鈥�
98h
TXSTA
CSRC
TX9
TXEN
SYNC
鈥�
BRGH
TRMT
TX9D
0000 -010
99h
SPBRG
Baud Rate Generator Register
0000 0000
9Ah
鈥�
Unimplemented
鈥�
9Bh
鈥�
Unimplemented
鈥�
9Ch
CMCON
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
0000 0111
9Dh
CVRCON
CVREN
CVROE
CVRR
鈥�
CVR3
CVR2
CVR1
CVR0
000- 0000
9Eh
ADRESL
A/D Result Register Low Byte
xxxx xxxx
9Fh
ADCON1
ADFM
ADCS2
鈥�
PCFG3
PCFG2
PCFG1
PCFG0
00-- 0000
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Details
on page:
Legend:
x
= unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as 鈥�0鈥�, r = reserved.
Shaded locations are unimplemented, read as 鈥�0鈥�.
Note
1:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter.
2:
Bits PSPIE and PSPIF are reserved on PIC16F873A/876A devices; always maintain these bits clear.
3:
These registers can be addressed from any bank.
4:
PORTD, PORTE, TRISD and TRISE are not implemented on PIC16F873A/876A devices, read as 鈥�0鈥�.
5:
Bit 4 of EEADRH implemented only on the PIC16F876A/877A devices.
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鍙冩暩(sh霉)鎻忚堪
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