- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗3819 > PIC16F876-20I/SP (Microchip Technology)IC MCU FLASH 8KX14 EE 28DIP PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | PIC16F876-20I/SP |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋佹暩(sh霉)锛� | 200/218闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MCU FLASH 8KX14 EE 28DIP |
| 鐢�(ch菐n)鍝佸煿瑷撴ā濉婏細 | Asynchronous Stimulus 8-bit PIC® Microcontroller Portfolio |
| 妯欐簴鍖呰锛� | 15 |
| 绯诲垪锛� | PIC® 16F |
| 鏍稿績铏曠悊鍣細 | PIC |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 20MHz |
| 閫ｉ€氭€э細 | I²C锛孲PI锛孶ART/USART |
| 澶栧湇瑷�(sh猫)鍌欙細 | 娆犲妾㈡脯/寰╀綅锛孭OR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 22 |
| 绋嬪簭瀛樺劜鍣ㄥ閲忥細 | 14KB锛�8K x 14锛� |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | 闁冨瓨 |
| EEPROM 澶�?銆�?/td> | 256 x 8 |
| RAM 瀹归噺锛� | 368 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 4 V ~ 5.5 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 5x10b |
| 鎸暕鍣ㄥ瀷锛� | 澶栭儴 |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 28-DIP锛�0.300"锛�7.62mm锛� |
| 鍖呰锛� | 绠′欢 |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�绗�80闋�绗�81闋�绗�82闋�绗�83闋�绗�84闋�绗�85闋�绗�86闋�绗�87闋�绗�88闋�绗�89闋�绗�90闋�绗�91闋�绗�92闋�绗�93闋�绗�94闋�绗�95闋�绗�96闋�绗�97闋�绗�98闋�绗�99闋�绗�100闋�绗�101闋�绗�102闋�绗�103闋�绗�104闋�绗�105闋�绗�106闋�绗�107闋�绗�108闋�绗�109闋�绗�110闋�绗�111闋�绗�112闋�绗�113闋�绗�114闋�绗�115闋�绗�116闋�绗�117闋�绗�118闋�绗�119闋�绗�120闋�绗�121闋�绗�122闋�绗�123闋�绗�124闋�绗�125闋�绗�126闋�绗�127闋�绗�128闋�绗�129闋�绗�130闋�绗�131闋�绗�132闋�绗�133闋�绗�134闋�绗�135闋�绗�136闋�绗�137闋�绗�138闋�绗�139闋�绗�140闋�绗�141闋�绗�142闋�绗�143闋�绗�144闋�绗�145闋�绗�146闋�绗�147闋�绗�148闋�绗�149闋�绗�150闋�绗�151闋�绗�152闋�绗�153闋�绗�154闋�绗�155闋�绗�156闋�绗�157闋�绗�158闋�绗�159闋�绗�160闋�绗�161闋�绗�162闋�绗�163闋�绗�164闋�绗�165闋�绗�166闋�绗�167闋�绗�168闋�绗�169闋�绗�170闋�绗�171闋�绗�172闋�绗�173闋�绗�174闋�绗�175闋�绗�176闋�绗�177闋�绗�178闋�绗�179闋�绗�180闋�绗�181闋�绗�182闋�绗�183闋�绗�184闋�绗�185闋�绗�186闋�绗�187闋�绗�188闋�绗�189闋�绗�190闋�绗�191闋�绗�192闋�绗�193闋�绗�194闋�绗�195闋�绗�196闋�绗�197闋�绗�198闋�绗�199闋�鐣跺墠绗�200闋�绗�201闋�绗�202闋�绗�203闋�绗�204闋�绗�205闋�绗�206闋�绗�207闋�绗�208闋�绗�209闋�绗�210闋�绗�211闋�绗�212闋�绗�213闋�绗�214闋�绗�215闋�绗�216闋�绗�217闋�绗�218闋�
PIC16F87X
DS30292C-page 80
2001 Microchip Technology Inc.
FIGURE 9-11:
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
9.2.9
I2C MASTER MODE START
CONDITION TIMING
To initiate a START condition, the user sets the START
condition enable bit, SEN (SSPCON2<0>). If the SDA
and SCL pins are sampled high, the baud rate genera-
tor is reloaded with the contents of SSPADD<6:0> and
starts its count. If SCL and SDA are both sampled high
when the baud rate generator times out (TBRG), the
SDA pin is driven low. The action of the SDA being
driven low while SCL is high is the START condition,
and causes the S bit (SSPSTAT<3>) to be set. Follow-
ing this, the baud rate generator is reloaded with the
contents of SSPADD<6:0> and resumes its count.
When the baud rate generator times out (TBRG), the
SEN bit (SSPCON2<0>) will be automatically cleared
by hardware. The baud rate generator is suspended,
leaving the SDA line held low, and the START condition
is complete.
9.2.9.1
WCOL Status Flag
If the user writes the SSPBUF when a START
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn鈥檛
occur).
FIGURE 9-12:
FIRST START BIT TIMING
SDA
SCL
SCL de-asserted but slave holds
DX-1
DX
BRG
SCL is sampled high, reload takes
place, and BRG starts its count
03h
02h
01h
00h (hold off)
03h
02h
Reload
BRG
Value
SCL low (clock arbitration)
SCL allowed to transition high
BRG decrements
(on Q2 and Q4 cycles)
Note:
If, at the beginning of START condition, the
SDA and SCL pins are already sampled
low, or if during the START condition the
SCL line is sampled low before the SDA
line is driven low, a bus collision occurs,
the Bus Collision Interrupt Flag (BCLIF) is
set, the START condition is aborted, and
the I2C module is reset into its IDLE state.
Note:
Because
queueing
of
events
is
not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the START
condition is complete.
SDA
SCL
S
TBRG
1st Bit
2nd Bit
TBRG
SDA = 1,
At completion of START bit,
SCL = 1
Write to SSPBUF occurs here
TBRG
Hardware clears SEN bit
TBRG
Write to SEN bit occurs here
Set S bit (SSPSTAT<3>)
and sets SSPIF bit
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| PIC24HJ128GP210-I/PF | IC PIC MCU FLASH 128KB 100TQFP |
| PIC18F2580-I/SP | IC PIC MCU FLASH 16KX16 28DIP |
| DSPIC33FJ128MC706-I/PT | IC DSPIC MCU/DSP 128K 64TQFP |
| PIC16F877-20/P | IC MCU FLASH 8KX14 EE 40DIP |
| PIC18LF2620-I/SO | IC MCU FLASH 32KX16 28SOIC |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| PIC16F87620SP | 鍒堕€犲晢:MICRO CHIP 鍔熻兘鎻忚堪:New |
| PIC16F876A-E/AP | 鍒堕€犲晢:Microchip Technology Inc 鍔熻兘鎻忚堪:MCU PICMICRO - PIC16FXXX FLASH *NIC* |
| PIC16F876A-E/ML | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 14KB 368 RAM 22 I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT |
| PIC16F876A-E/SO | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 14KB 368 RAM 22 I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT |
| PIC16F876A-E/SP | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 14KB 368 RAM 22 I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT |
鐧�(f膩)甯冪穵鎬ラ噰璩�锛�3鍒嗛悩宸﹀彸鎮ㄥ皣寰楀埌鍥炲京銆�
