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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� PIC16F874-04I/P
寤犲晢锛� Microchip Technology
鏂囦欢闋佹暩(sh霉)锛� 101/218闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC MCU FLASH 4KX14 EE 40DIP
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 10
绯诲垪锛� PIC® 16F
鏍稿績铏曠悊鍣細 PIC
鑺珨灏哄锛� 8-浣�
閫熷害锛� 4MHz
閫i€氭€э細 I²C锛孲PI锛孶ART/USART
澶栧湇瑷�(sh猫)鍌欙細 娆犲妾㈡脯(c猫)/寰�(f霉)浣�锛孭OR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 33
绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 7KB锛�4K x 14锛�
绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 闁冨瓨
EEPROM 澶�?銆�?/td> 128 x 8
RAM 瀹归噺锛� 192 x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 4 V ~ 5.5 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 8x10b
鎸暕鍣ㄥ瀷锛� 澶栭儴
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 40-DIP锛�0.600"锛�15.24mm锛�
鍖呰锛� 绠′欢
閰嶇敤锛� 444-1001-ND - DEMO BOARD FOR PICMICRO MCU
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2001 Microchip Technology Inc.
DS30292C-page 17
PIC16F87X
Bank 2
100h(3)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
101h
TMR0
Timer0 Module Register
xxxx xxxx
102h(3)
PCL
Program Counter鈥檚 (PC) Least Significant Byte
0000 0000
103h(3)
STATUS
IRP
RP1
RP0
TO
PD
ZDC
C
0001 1xxx
104h(3)
FSR
Indirect Data Memory Address Pointer
xxxx xxxx
105h
鈥�
Unimplemented
鈥�
106h
PORTB
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx
107h
鈥�
Unimplemented
鈥�
108h
鈥�
Unimplemented
鈥�
109h
鈥�
Unimplemented
鈥�
10Ah(1,3)
PCLATH
鈥�
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
10Bh(3)
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
10Ch
EEDATA
EEPROM Data Register Low Byte
xxxx xxxx
10Dh
EEADR
EEPROM Address Register Low Byte
xxxx xxxx
10Eh
EEDATH
鈥�
EEPROM Data Register High Byte
xxxx xxxx
10Fh
EEADRH
鈥�
EEPROM Address Register High Byte
xxxx xxxx
Bank 3
180h(3)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
181h
OPTION_REG
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
182h(3)
PCL
Program Counter (PC) Least Significant Byte
0000 0000
183h(3)
STATUS
IRP
RP1
RP0
TO
PD
ZDC
C
0001 1xxx
184h(3)
FSR
Indirect Data Memory Address Pointer
xxxx xxxx
185h
鈥�
Unimplemented
鈥�
186h
TRISB
PORTB Data Direction Register
1111 1111
187h
鈥�
Unimplemented
鈥�
188h
鈥�
Unimplemented
鈥�
189h
鈥�
Unimplemented
鈥�
18Ah(1,3)
PCLATH
鈥�
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
18Bh(3)
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
18Ch
EECON1
EEPGD
鈥�
WRERR
WREN
WR
RD
x--- x000
18Dh
EECON2
EEPROM Control Register2 (not a physical register)
---- ----
18Eh
鈥�
Reserved maintain clear
0000 0000
鈥�
18Fh
鈥�
Reserved maintain clear
0000 0000
鈥�
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Details
on
page:
Legend:
x
= unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as 鈥�0鈥�.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
2: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear.
3: These registers can be addressed from any bank.
4: PORTD, PORTE, TRISD, and TRISE are not physically implemented on PIC16F873/876 devices; read as 鈥�0鈥�.
5: PIR2<6> and PIE2<6> are reserved on these devices; always maintain these bits clear.
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