132
8048C–AVR–02/12
ATtiny43U
trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running
mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set
.
16.13.5
DIDR0 – Digital Input Disable Register 0
Bits 3:0 – ADC3D:ADC0D: ADC[3:0] Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-
abled. The corresponding PIN register bit will always read as zero when this bit is set. When an
analog signal is applied to the ADC[3:0] pin and the digital input from this pin is not needed, this
bit should be written logic one to reduce power consumption in the digital input buffer.
Table 16-6.
ADC Auto Trigger Source Selections
ADTS2
ADTS1
ADTS0
Trigger Source
0
Free Running mode
0
1
Analog Comparator
0
1
0
External Interrupt Request 0
0
1
Timer/Counter0 Compare Match A
1
0
Timer/Counter0 Overflow
1
0
1
Timer/Counter1 Compare Match A
1
0
Timer/Counter1 Overflow
1
Timer/Counter1 Compare Match B
Bit
765
432
10
––
AIN1D
AIN0D
ADC3D
ADC2D
ADC1D
ADC0D
DIDR0
Read/Write
R
R/W
Initial Value
0