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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� PIC16F871-I/P
寤犲晢锛� Microchip Technology
鏂囦欢闋佹暩(sh霉)锛� 52/143闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC MCU FLASH 2KX14 EE 40DIP
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 10
绯诲垪锛� PIC® 16F
鏍稿績铏曠悊鍣細 PIC
鑺珨灏哄锛� 8-浣�
閫熷害锛� 20MHz
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澶栧湇瑷�(sh猫)鍌欙細 娆犲妾㈡脯/寰�(f霉)浣�锛孭OR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 33
绋嬪簭瀛樺劜鍣ㄥ閲忥細 3.5KB锛�2K x 14锛�
绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 闁冨瓨
EEPROM 澶у皬锛� 64 x 8
RAM 瀹归噺锛� 128 x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 4 V ~ 5.5 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 8x10b
鎸暕鍣ㄥ瀷锛� 澶栭儴
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 40-DIP锛�0.600"锛�15.24mm锛�
鍖呰锛� 绠′欢
鐢�(ch菐n)鍝佺洰閷勯爜闈細 639 (CN2011-ZH PDF)
閰嶇敤锛� I3-DB16F871-ND - BOARD DAUGHTER ICEPIC3
444-1001-ND - DEMO BOARD FOR PICMICRO MCU
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PIC16F870/871
DS30569B-page 14
2003 Microchip Technology Inc.
Bank 1
80h(4)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
81h
OPTION_REG
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
82h(4)
PCL
Program Counter's (PC) Least Significant Byte
0000 0000
83h(4)
STATUS
IRP
RP1
RP0
TO
PD
ZDC
C
0001 1xxx
000q quuu
84h(4)
FSR
Indirect Data Memory Address Pointer
xxxx xxxx
uuuu uuuu
85h
TRISA
鈥�
PORTA Data Direction Register
--11 1111
86h
TRISB
PORTB Data Direction Register
1111 1111
87h
TRISC
PORTC Data Direction Register
1111 1111
88h(5)
TRISD
PORTD Data Direction Register
1111 1111
89h(5)
TRISE
IBF
OBF
IBOV
PSPMODE
鈥�
PORTE Data Direction Bits
0000 -111
8Ah(1,4)
PCLATH
鈥�
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
8Bh(4)
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
8Ch
PIE1
PSPIE(3)
ADIE
RCIE
TXIE
鈥�
CCP1IE
TMR2IE
TMR1IE
0000 -000
8Dh
PIE2
鈥�
EEIE
鈥�
---0 ----
8Eh
PCON
鈥�
鈥擯OR
BOR
---- --qq
---- --uu
8Fh
鈥�
Unimplemented
鈥�
90h
鈥�
Unimplemented
鈥�
91h
鈥�
Unimplemented
鈥�
92h
PR2
Timer2 Period Register
1111 1111
93h
鈥�
Unimplemented
鈥�
94h
鈥�
Unimplemented
鈥�
95h
鈥�
Unimplemented
鈥�
96h
鈥�
Unimplemented
鈥�
97h
鈥�
Unimplemented
鈥�
98h
TXSTA
CSRC
TX9
TXEN
SYNC
鈥�
BRGH
TRMT
TX9D
0000 -010
99h
SPBRG
Baud Rate Generator Register
0000 0000
9Ah
鈥�
Unimplemented
鈥�
9Bh
鈥�
Unimplemented
鈥�
9Ch
鈥�
Unimplemented
鈥�
9Dh
鈥�
Unimplemented
鈥�
9Eh
ADRESL
A/D Result Register Low Byte
xxxx xxxx
uuuu uuuu
9Fh
ADCON1
ADFM
鈥�
PCFG3
PCFG2
PCFG1
PCFG0
0--- 0000
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
RESETS(2)
Legend:
x
= unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as 鈥�0鈥�.
Note
1:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
2:
Other (non Power-up) Resets include external RESET through MCLR and Watchdog Timer Reset.
3:
Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4:
These registers can be addressed from any bank.
5:
PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices, read as 鈥�0鈥�.
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