SLOW RISE TIME (MCLR TIED TO VDD
參數(shù)資料
型號(hào): PIC16F871-E/L
廠商: Microchip Technology
文件頁(yè)數(shù): 142/143頁(yè)
文件大小: 0K
描述: IC MCU CMOS 20MHZ 2K FLSH 44PLCC
標(biāo)準(zhǔn)包裝: 27
系列: PIC® 16F
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
連通性: UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 33
程序存儲(chǔ)器容量: 3.5KB(2K x 14)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 64 x 8
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 外部
工作溫度: -40°C ~ 125°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 管件
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PIC16F870/871
DS30569B-page 96
2003 Microchip Technology Inc.
FIGURE 11-8:
SLOW RISE TIME (MCLR TIED TO VDD)
11.10 Interrupts
The PIC16F870/871 family has up to 14 sources of
interrupt. The Interrupt Control register (INTCON)
records individual interrupt requests in flag bits. It also
has individual and global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>),
enables (if set) all unmasked interrupts, or disables (if
cleared) all interrupts. When bit GIE is enabled, and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in vari-
ous
registers.
Individual
interrupt
bits
are
set,
regardless of the status of the GIE bit. The GIE bit is
cleared on RESET.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine as well as sets the GIE bit, which
re-enables interrupts.
The RB0/INT pin interrupt, the RB port change
interrupt, and the TMR0 overflow interrupt flags are
contained in the INTCON register.
The peripheral interrupt flags are contained in the spe-
cial function registers, PIR1 and PIR2. The correspond-
ing interrupt enable bits are contained in special
function registers, PIE1 and PIE2, and the peripheral
interrupt enable bit is contained in special function
register, INTCON.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs. The latency
is the same for one or two-cycle instructions. Individual
interrupt flag bits are set, regardless of the status of
their corresponding mask bit, PEIE bit, or GIE bit.
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
0V
1V
5V
TPWRT
TOST
Note:
Individual interrupt flag bits are set,
regardless
of
the
status
of
their
corresponding mask bit, or the GIE bit.
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