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    參數(shù)資料
    型號: PIC16F84A-04/SO
    廠商: Microchip Technology
    文件頁數(shù): 78/81頁
    文件大小: 0K
    描述: IC MCU FLASH 1KX14 EE 18SOIC
    產(chǎn)品培訓模塊: Asynchronous Stimulus
    8-bit PIC® Microcontroller Portfolio
    標準包裝: 42
    系列: PIC® 16F
    核心處理器: PIC
    芯體尺寸: 8-位
    速度: 4MHz
    外圍設(shè)備: POR,WDT
    輸入/輸出數(shù): 13
    程序存儲器容量: 1.75KB(1K x 14)
    程序存儲器類型: 閃存
    EEPROM 大?。?/td> 64 x 8
    RAM 容量: 68 x 8
    電壓 - 電源 (Vcc/Vdd): 4 V ~ 5.5 V
    振蕩器型: 外部
    工作溫度: 0°C ~ 70°C
    封裝/外殼: 18-SOIC(0.295",7.50mm 寬)
    包裝: 管件
    產(chǎn)品目錄頁面: 638 (CN2011-ZH PDF)
    配用: XLT18SO-1-ND - SOCKET TRANSITION 18SOIC 300MIL
    I3-DB16F84A-ND - BOARD DAUGHTER ICEPIC3
    309-1075-ND - ADAPTER 18-SOIC TO 18-SOIC
    309-1011-ND - ADAPTER 18-SOIC TO 18-DIP
    309-1010-ND - ADAPTER 18-SOIC TO 18-DIP
    AC164010-ND - MODULE SKT PROMATEII DIP/SOIC
    PIC16F84A
    DS35007B-page 6
    2001 Microchip Technology Inc.
    2.2
    Data Memory Organization
    The data memory is partitioned into two areas. The first
    is the Special Function Registers (SFR) area, while the
    second is the General Purpose Registers (GPR) area.
    The SFRs control the operation of the device.
    Portions of data memory are banked. This is for both
    the SFR area and the GPR area. The GPR area is
    banked to allow greater than 116 bytes of general
    purpose RAM. The banked areas of the SFR are for the
    registers that control the peripheral functions. Banking
    requires the use of control bits for bank selection.
    These control bits are located in the STATUS Register.
    Figure 2-2 shows the data memory map organization.
    Instructions MOVWF and MOVF can move values from
    the W register to any location in the register file (“F”),
    and vice-versa.
    The entire data memory can be accessed either
    directly using the absolute address of each register file
    or indirectly through the File Select Register (FSR)
    (Section 2.5). Indirect addressing uses the present
    value of the RP0 bit for access into the banked areas of
    data memory.
    Data memory is partitioned into two banks which
    contain the general purpose registers and the special
    function registers. Bank 0 is selected by clearing the
    RP0 bit (STATUS<5>). Setting the RP0 bit selects Bank
    1. Each Bank extends up to 7Fh (128 bytes). The first
    twelve locations of each Bank are reserved for the
    Special Function Registers. The remainder are Gen-
    eral Purpose Registers, implemented as static RAM.
    2.2.1
    GENERAL PURPOSE REGISTER
    FILE
    Each General Purpose Register (GPR) is 8-bits wide
    and is accessed either directly or indirectly through the
    The GPR addresses in Bank 1 are mapped to
    addresses in Bank 0. As an example, addressing loca-
    tion 0Ch or 8Ch will access the same GPR.
    FIGURE 2-2:
    REGISTER FILE MAP -
    PIC16F84A
    File Address
    00h
    01h
    02h
    03h
    04h
    05h
    06h
    07h
    08h
    09h
    0Ah
    0Bh
    0Ch
    7Fh
    80h
    81h
    82h
    83h
    84h
    85h
    86h
    87h
    88h
    89h
    8Ah
    8Bh
    8Ch
    FFh
    Bank 0
    Bank 1
    Indirect addr.(1)
    TMR0
    OPTION_REG
    PCL
    STATUS
    FSR
    PORTA
    PORTB
    EEDATA
    EEADR
    PCLATH
    INTCON
    68
    General
    Purpose
    Registers
    (SRAM)
    PCL
    STATUS
    FSR
    TRISA
    TRISB
    EECON1
    EECON2(1)
    PCLATH
    INTCON
    Mapped
    in Bank 0
    Unimplemented data memory location, read as ’0’.
    File Address
    Note
    1:
    Not a physical register.
    CFh
    D0h
    4Fh
    50h
    (accesses)
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