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| 鍨嬭櫉锛� | PIC16F84A-04/P |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋佹暩(sh霉)锛� | 24/81闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MCU FLASH 1KX14 EE 18DIP |
| 鐢�(ch菐n)鍝佸煿瑷撴ā濉婏細 | Asynchronous Stimulus 8-bit PIC® Microcontroller Portfolio |
| 妯欐簴鍖呰锛� | 25 |
| 绯诲垪锛� | PIC® 16F |
| 鏍稿績铏曠悊鍣細 | PIC |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 4MHz |
| 澶栧湇瑷倷锛� | POR锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 13 |
| 绋嬪簭瀛樺劜鍣ㄥ閲忥細 | 1.75KB锛�1K x 14锛� |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | 闁冨瓨 |
| EEPROM 澶�?銆�?/td> | 64 x 8 |
| RAM 瀹归噺锛� | 68 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 4 V ~ 5.5 V |
| 鎸暕鍣ㄥ瀷锛� | 澶栭儴 |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 灏佽/澶栨锛� | 18-DIP锛�0.300"锛�7.62mm锛� |
| 鍖呰锛� | 绠′欢 |
| 鐢�(ch菐n)鍝佺洰閷勯爜闈細 | 638 (CN2011-ZH PDF) |
| 閰嶇敤锛� | I3-DB16F84A-ND - BOARD DAUGHTER ICEPIC3 DVA16XP180-ND - ADAPTER DEVICE FOR MPLAB-ICE AC164010-ND - MODULE SKT PROMATEII DIP/SOIC |
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PIC16F84A
DS35007B-page 28
2001 Microchip Technology Inc.
FIGURE 6-9:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD):
SLOW VDD RISE TIME
6.7
Time-out Sequence and
Power-down Status Bits (TO/PD)
sequence is as follows:
1.
PWRT time-out is invoked after a POR has
expired.
2.
Then, the OST is activated.
The total time-out will vary based on oscillator configu-
ration and PWRTE configuration bit status. For exam-
ple, in RC mode with the PWRT disabled, there will be
no time-out at all.
TABLE 6-5:
TIME-OUT IN VARIOUS
SITUATIONS
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high, execution will begin immediately
(Figure 6-6). This is useful for testing purposes or to
synchronize more than one PIC16F84A device when
operating in parallel.
Table 6-6 shows the significance of the TO and PD bits.
Table 6-3 lists the RESET conditions for some special
registers, while Table 6-4 lists the RESET conditions
for all the registers.
TABLE 6-6:
STATUS BITS AND THEIR
SIGNIFICANCE
VDD
MCLR
V1
When VDD rises very slowly, it is possible that the TPWRT time-out and TOST time-out will expire before VDD
has reached its final value. In this example, the chip will reset properly if, and only if, V1
鈮� VDD min.
INTERNAL POR
TPWRT
TOST
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
Oscillator
Configuration
Power-up
Wake-up
from
SLEEP
PWRT
Enabled
PWRT
Disabled
XT, HS, LP
72 ms +
1024TOSC
RC
72 ms
鈥斺€�
TO
PD
Condition
11
Power-on Reset
0x
Illegal, TO is set on POR
x0
Illegal, PD is set on POR
01
WDT Reset (during normal operation)
00
WDT Wake-up
11
MCLR during normal operation
10
MCLR during SLEEP or interrupt
wake-up from SLEEP
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