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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | PIC16F77T-I/PTG |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋佹暩(sh霉)锛� | 10/104闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC MCU FLASH 8KX14 W/AD 44TQFP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1,200 |
| 绯诲垪锛� | PIC® 16F |
| 鏍稿績铏曠悊鍣細 | PIC |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 20MHz |
| 閫ｉ€氭€э細 | I²C锛孲PI锛孶ART/USART |
| 澶栧湇瑷�(sh猫)鍌欙細 | 娆犲妾㈡脯(c猫)/寰�(f霉)浣�锛孭OR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 33 |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 | 14KB锛�8K x 14锛� |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 | 闁冨瓨 |
| RAM 瀹归噺锛� | 368 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 4 V ~ 5.5 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 8x8b |
| 鎸暕鍣ㄥ瀷锛� | 澶栭儴 |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 44-TQFP |
| 鍖呰锛� | 甯跺嵎 (TR) |
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PIC18F45J10 FAMILY
DS39682E-page 160
2009 Microchip Technology Inc.
REGISTER 16-3:
SSPxSTAT: MSSPx STATUS REGISTER (I2C MODE)
R/W-0
R-0
R0
R-0
SMP
CKE
D/A
P(1)
S(1)
R/W
UA
BF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as 鈥�0鈥�
-n = Value at POR
鈥�1鈥� = Bit is set
鈥�0鈥� = Bit is cleared
x = Bit is unknown
bit 7
SMP:
Slew Rate Control bit
In Master or Slave mode:
1
= Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)
0
= Slew rate control enabled for High-Speed mode (400 kHz)
bit 6
CKE:
SMBus Select bit
In Master or Slave mode:
1
= Enable SMBus specific inputs
0
= Disable SMBus specific inputs
bit 5
D/A:
Data/Address bit
In Master mode:
Reserved.
In Slave mode:
1
= Indicates that the last byte received or transmitted was data
0
= Indicates that the last byte received or transmitted was address
bit 4
P:
Stop bit(1)
1
= Indicates that a Stop bit has been detected last
0
= Stop bit was not detected last
bit 3
S:
Start bit(1)
1
= Indicates that a Start bit has been detected last
0
= Start bit was not detected last
bit 2
R/W:
Read/Write Information bit (I2C mode only)
In Slave mode:(2)
1
= Read
0
= Write
In Master mode:(3)
1
= Transmit is in progress
0
= Transmit is not in progress
bit 1
UA:
Update Address bit (10-Bit Slave mode only)
1
= Indicates that the user needs to update the address in the SSPxADD register
0
= Address does not need to be updated
bit 0
BF:
Buffer Full Status bit
In Transmit mode:
1
= SSPxBUF is full
0
= SSPxBUF is empty
In Receive mode:
1
= SSPxBUF is full (does not include the ACK and Stop bits)
0
= SSPxBUF is empty (does not include the ACK and Stop bits)
Note 1:
This bit is cleared on Reset and when SSPEN is cleared.
2:
This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next Start bit, Stop bit or not ACK bit.
3:
ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode.
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| PIC16F785-E/ML | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 3.5 KB 128 RAM 18I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| PIC16F785-E/P | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 14KB 368 RAM 33 I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
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| PIC16F785-E/SS | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 3.5KB FL 128R 18 I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| PIC16F785-I/ML | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 3.5 KB 128 RAM 18I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
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