100h(4) INDF Addressing this location " />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� PIC16F76-I/SP
寤犲晢锛� Microchip Technology
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鏂囦欢澶у皬锛� 0K
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8-bit PIC® Microcontroller Portfolio
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鐢�(ch菐n)鍝佺洰閷勯爜闈細 641 (CN2011-ZH PDF)
PIC16F7X
DS30325B-page 18
2002 Microchip Technology Inc.
Bank 2
100h(4)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
101h
TMR0
Timer0 Module Register
xxxx xxxx
102h(4)
PCL
Program Counter (PC) Least Significant Byte
0000 0000
103h(4)
STATUS
IRP
RP1
RP0
TO
PD
ZDC
C
0001 1xxx
104h(4)
FSR
Indirect Data Memory Address Pointer
xxxx xxxx
105h
鈥�
Unimplemented
鈥�
106h
PORTB
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx
107h
鈥�
Unimplemented
鈥�
108h
鈥�
Unimplemented
鈥�
109h
鈥�
Unimplemented
鈥�
10Ah(1,4) PCLATH
鈥�
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
10Bh(4)
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
10Ch
PMDATA
Data Register Low Byte
xxxx xxxx
10Dh
PMADR
Address Register Low Byte
xxxx xxxx
10Eh
PMDATH
鈥�
Data Register High Byte
xxxx xxxx
10Fh
PMADRH
鈥�
Address Register High Byte
xxxx xxxx
Bank 3
180h(4)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
181h
OPTION_REG
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
182h(4)
PCL
Program Counter (PC) Least Significant Byte
0000 0000
183h(4)
STATUS
IRP
RP1
RP0
TO
PD
ZDC
C
0001 1xxx
184h(4)
FSR
Indirect Data Memory Address Pointer
xxxx xxxx
185h
鈥�
Unimplemented
鈥�
186h
TRISB
PORTB Data Direction Register
1111 1111
187h
鈥�
Unimplemented
鈥�
188h
鈥�
Unimplemented
鈥�
189h
鈥�
Unimplemented
鈥�
18Ah(1,4) PCLATH
鈥�
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
18Bh(4)
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
18Ch
PMCON1
鈥� (6)
鈥�
RD
1--- ---0
18Dh
鈥�
Unimplemented
鈥�
18Eh
鈥�
Reserved maintain clear
0000 0000
18Fh
鈥�
Reserved maintain clear
0000 0000
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Details
on page
Legend:
x
= unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as 鈥�0鈥�.
Note
1:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter during branches (CALL or GOTO).
2:
Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
3:
Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4:
These registers can be addressed from any bank.
5:
PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as 鈥�0鈥�.
6:
This bit always reads as a 鈥�1鈥�.
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