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2004 Microchip Technology Inc.
DS30498C-page 19
PIC16F7X7
Bank 1
80h(4)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000
81h
OPTION_REG
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
82h(4)
PCL
Program Counter鈥檚 (PC) Least Significant Byte
0000 0000
83h(4)
STATUS
IRP
RP1
RP0
TO
PD
ZDC
C
0001 1xxx
84h(4)
FSR
Indirect Data Memory Address Pointer
xxxx xxxx
85h
TRISA
PORTA Data Direction Register
1111 1111
86h
TRISB
PORTB Data Direction Register
1111 1111
87h
TRISC
PORTC Data Direction Register
1111 1111
88h(5)
TRISD
PORTD Data Direction Register
1111 1111
89h(5)
TRISE
IBF(5)
OBF(5)
IBOV(5)
PSPMODE(5)
鈥�(8)
PORTE Data Direction bits
0000 1111
8Ah(1,4)
PCLATH
鈥�
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
8Bh(4)
INTCON
GIE
PEIE
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
8Ch
PIE1
PSPIE(3)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
8Dh
PIE2
OSFIE
CMIE
LVDIE
鈥擝CLIE
鈥�
CCP3IE
CCP2IE
000- 0-00
8Eh
PCON
鈥�
SBOREN
POR
BOR
---- -1qq
8Fh
OSCCON
鈥�
IRCF2
IRCF1
IRCF0
OSTS(7)
IOFS
SCS1
SCS0
-000 1000
90h
OSCTUNE
鈥�
TUN5
TUN4
TUN3
TUN2
TUN1
TUN0
--00 0000
91h
SSPCON2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
0000 0000
92h
PR2
Timer2 Period Register
1111 1111
93h
SSPADD
Synchronous Serial Port (I2C mode) Address Register
0000 0000
94h
SSPSTAT
SMP
CKE
D/A
PS
R/W
UA
BF
0000 0000
95h
CCPR3L
Capture/Compare/PWM Register 3 (LSB)
xxxx xxxx
96h
CCPR3H
Capture/Compare/PWM Register 3 (MSB)
xxxx xxxx
97h
CCP3CON
鈥�
CCP3X
CCP3Y
CCP3M3
CCP3M2
CCP3M1
CCP3M0 --00 0000
98h
TXSTA
CSRC
TX9
TXEN
SYNC
鈥擝RGH
TRMT
TX9D
0000 -010
99h
SPBRG
Baud Rate Generator Register
0000 0000
9Ah
鈥�
Unimplemented
鈥�
9Bh
ADCON2
鈥�
ACQT2
ACQT1
ACQT0
鈥�
--00 0---
9Ch
CMCON
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
0000 0111
9Dh
CVRCON
CVREN
CVROE
CVRR
鈥�
CVR3
CVR2
CVR1
CVR0
000- 0000
9Eh
ADRESL
A/D Result Register Low Byte
xxxx xxxx
9Fh
ADCON1
ADFM
ADCS2
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
0000 0000
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Details
on page
Legend:
x
= unknown, u = unchanged, q = value depends on condition, 鈥� = unimplemented, read as 鈥�0鈥�, r = reserved.
Shaded locations are unimplemented, read as 鈥�0鈥�.
Note 1:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> bits, whose contents
are transferred to the upper byte of the program counter during branches (CALL or GOTO).
2:
Other (non Power-up) Resets include external Reset through MCLR and Watchdog Timer Reset.
3:
Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4:
These registers can be addressed from any bank.
5:
PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices (except for RE3), read as 鈥�0鈥�.
6:
This bit always reads as a 鈥�1鈥�.
7:
OSCCON<OSTS> bit resets to 鈥�0鈥� with dual-speed start-up and LP, HS or HS-PLL selected as the oscillator.
8:
RE3 is an input only. The state of the TRISE3 bit has no effect and will always read 鈥�1鈥�.
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