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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | PIC16F72-I/SS |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋佹暩(sh霉)锛� | 35/136闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC PIC MCU FLASH 2KX14 28-SSOP |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Asynchronous Stimulus 8-bit PIC® Microcontroller Portfolio |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 47 |
| 绯诲垪锛� | PIC® 16F |
| 鏍稿績铏曠悊鍣細 | PIC |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 20MHz |
| 閫ｉ€氭€э細 | I²C锛孲PI |
| 澶栧湇瑷�(sh猫)鍌欙細 | 娆犲妾㈡脯/寰�(f霉)浣�锛孭OR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 22 |
| 绋嬪簭瀛樺劜鍣ㄥ閲忥細 | 3.5KB锛�2K x 14锛� |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | 闁冨瓨 |
| RAM 瀹归噺锛� | 128 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 4 V ~ 5.5 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 5x8b |
| 鎸暕鍣ㄥ瀷锛� | 澶栭儴 |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 28-SSOP锛�0.209"锛�5.30mm 瀵級 |
| 鍖呰锛� | 绠′欢 |
| 鐢�(ch菐n)鍝佺洰閷勯爜闈細 | 639 (CN2011-ZH PDF) |
| 閰嶇敤锛� | AC164307-ND - MODULE SKT FOR PM3 28SSOP |
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2007 Microchip Technology Inc.
DS39597C-page 11
PIC16F72
Bank 2
100h(1)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000
101h
TMR0
Timer0 Module鈥檚 Register
xxxx xxxx
102h(1
PCL
Program Counter's (PC) Least Significant Byte
0000 0000
103h(1)
STATUS
IRP
RP1
RP0
TO
PD
ZDC
C
0001 1xxx
104h(1)
FSR
Indirect Data Memory Address Pointer
xxxx xxxx
105h
鈥�
Unimplemented
鈥�
106h
PORTB
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx
107h
鈥�
Unimplemented
鈥�
108h
鈥�
Unimplemented
鈥�
109h
鈥�
Unimplemented
鈥�
10Ah(1,2) PCLATH
鈥�
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
10Bh(1)
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
10Ch
PMDATL
Data Register Low Byte
xxxx xxxx
10Dh
PMADRL
Address Register Low Byte
xxxx xxxx
10Eh
PMDATH
鈥�
Data Register High Byte
--xx xxxx
10Fh
PMADRH
鈥�
Address Register High Byte
---x xxxx
Bank 3
180h(1)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000
181h
OPTION
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
182h(1)
PCL
Program Counter's (PC) Least Significant Byte
0000 0000
183h(1)
STATUS
IRP
RP1
RP0
TO
PD
ZDC
C
0001 1xxx
184h(1)
FSR
Indirect Data Memory Address Pointer
xxxx xxxx
185h
鈥�
Unimplemented
鈥�
186h
TRISB
PORTB Data Direction Register
1111 1111
187h
鈥�
Unimplemented
鈥�
188h
鈥�
Unimplemented
鈥�
189h
鈥�
Unimplemented
鈥�
18Ah(1,2) PCLATH
鈥�
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
18Bh(1)
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
18Ch
PMCON1
鈥� (3)
鈥�
鈥擱D
1--- ---0
18Dh
鈥�
Unimplemented
鈥�
18Eh
鈥�
Reserved, maintain clear
0000 0000
鈥�
18Fh
鈥�
Reserved, maintain clear
0000 0000
鈥�
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details on
page:
Legend:
x
= unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as 鈥�0鈥�, r = reserved.
Shaded locations are unimplemented, read as 鈥�0鈥�.
Note
1:
These registers can be addressed from any bank.
2:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
3:
This bit always reads as a 鈥�1鈥�.
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