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參數(shù)資料
| 型號： | PIC16F639-E/SS |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 22/74頁 |
| 文件大小： | 0K |
| 描述： | IC MCU FLASH 2KX14 20SSOP |
| 標準包裝： | 67 |
| 系列： | PIC® 16F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 外圍設備： | 欠壓檢測/復位，LVD，POR，WDT |
| 輸入/輸出數(shù)： | 11 |
| 程序存儲器容量： | 3.5KB（2K x 14） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 128 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2 V ~ 3.6 V |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 20-SSOP（0.209"，5.30mm 寬） |
| 包裝： | 管件 |
| 配用： | XLT20SS1-1-ND - SOCKET TRANSITION 20DIP 20SSOP AC162066-ND - HEADER INTRFC MPLAB ICD2 20PIN |
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Micrel, Inc.
KSZ8841-PMQL
October 2007
29
M9999-100407-1.5
Configuration ID Register (CFID Offset 00H)
The CFID register identifies the KSZ8841-PMQL. The following table shows the CFID register bit fields.
Bit
Default
Description
31 - 16
0x8841
Device ID
15 - 0
0x16C6
Vendor ID
Specifies the manufacturer of the KSZ8841-PMQL.
The following table shows the access rules of the register.
Command and Status Configuration Register (CFCS Offset 04H)
The CFCS register is divided into two sections: a command register (CFCS[15:0]) and a status register (CFCS[31:16]).
The command register provides control of the KSZ8841-PMQL’s ability to generate and respond to PCI cycles. When 0
is written to this register, the KSZ8841-PMQL logically disconnects from the PCI bus for all accesses except
configuration accesses.
The status register records status information for the PCI bus-related events. The CFCS status bits are not cleared
when they are read. Writing 1 to these bits clears them; writing 0 has no effect.
The following table describes the CFCS register bit fields.
Bit
Type
Default
Description
31
Status
0
Detected Parity Error
When set, indicates that the KSZ8841-PMQL detected a parity
error, even if parity error handling is disabled in parity error
response (CFCS[6]).
30
Status
0
Signal System Error
When set, indicates that the KSZ8841-PMQL asserted the system
error SERR_N pin.
29
Status
0
Received Master Abort
When set, indicates that the KSZ8841-PMQL terminated a master
transaction with master abort.
28
Status
0
Received Target Abort
When set, indicates that the KSZ8841-PMQL master transaction
was terminated due to a target abort.
27
Status
0
Target Abort
This bit is set by KSZ8841-PMQL whenever it terminates with a
Target Abort. The CSR registers are all 32-bit Little Endian format.
For PCI register Read cycles, the KSZ8841-PMQL allows any
different combination of CBEN. For PCI register bus cycles, only
byte, word (16-bit), or Dword (32-bit) accesses are allowed. Any
other combination is illegal and is target aborted.
26 - 25
Status
01
Device Select Timing
Indicates the timing of the assertion of device select(DEVSEL_N).
These bits are fixed at 01, which indicates a medium assertion of
DEVSEL_N.
Category
Description
Value after hardware reset
0x884116C6
Write access rules
Write has no effect on the KSZ8841-PMQL.
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