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| 鍨嬭櫉锛� | PIC16F628-20/SS |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋佹暩(sh霉)锛� | 168/170闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MCU FLASH 2KX14 COMP 20SSOP |
| 鐢�(ch菐n)鍝佸煿瑷撴ā濉婏細 | Asynchronous Stimulus 8-bit PIC® Microcontroller Portfolio |
| 妯欐簴鍖呰锛� | 67 |
| 绯诲垪锛� | PIC® 16F |
| 鏍稿績铏曠悊鍣細 | PIC |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 20MHz |
| 閫ｉ€氭€э細 | UART/USART |
| 澶栧湇瑷倷锛� | 娆犲妾㈡脯/寰╀綅锛孭OR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 16 |
| 绋嬪簭瀛樺劜鍣ㄥ閲忥細 | 3.5KB锛�2K x 14锛� |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | 闁冨瓨 |
| EEPROM 澶�?銆�?/td> | 128 x 8 |
| RAM 瀹归噺锛� | 224 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 3 V ~ 5.5 V |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 灏佽/澶栨锛� | 20-SSOP锛�0.209"锛�5.30mm 瀵級 |
| 鍖呰锛� | 绠′欢 |
| 閰嶇敤锛� | XLT20SS-1-ND - SOCKET TRANSITION 18DIP 20SSOP AC164307-ND - MODULE SKT FOR PM3 28SSOP |
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2003 Microchip Technology Inc.
Preliminary
DS40300C-page 95
PIC16F62X
14.2.6
INTERNAL 4 MHZ OSCILLATOR
The internal RC oscillator provides a fixed 4 MHz
(nominal) system clock at V
DD = 5V and 25
掳C, see
鈥淓lectrical Specifications鈥� section for information on
variation over voltage and temperature.
14.2.7
CLKOUT
The PIC16F62X can be configured to provide a clock
out signal by programming the configuration word. The
oscillator frequency, divided by 4 can be used for test
purposes or to synchronize other logic.
14.3
Special Feature: Dual Speed
Oscillator Modes
A software programmable Dual Speed Oscillator mode
is provided when the PIC16F62X is configured in either
ER or INTRC Oscillator modes. This feature allows
users to dynamically toggle the oscillator speed
between 4 MHz and 37 kHz. In ER mode, the 4 MHz
setting will vary depending on the value of the external
resistor. Also in ER mode, the 37 kHz operation is fixed
and does not vary with resistor value. Applications that
require low current power savings, but cannot tolerate
putting the part into SLEEP, may use this mode.
The OSCF bit in the PCON register is used to control
Dual Speed mode. See Section 3.2.2.6, Register 3-4.
14.4
RESET
The PIC16F62X differentiates between various kinds of
RESET:
a)
Power-on Reset (POR)
b)
MCLR Reset during normal operation
c)
MCLR Reset during SLEEP
d)
WDT Reset (normal operation)
e)
WDT Wake-up (SLEEP)
f)
Brown-out Detect (BOD)
Some registers are not affected in any RESET condi-
tion; their status is unknown on POR and unchanged in
any other RESET. Most other registers are reset to a
鈥淩ESET state鈥� on Power-on Reset, MCLR Reset, WDT
Reset and MCLR Reset during SLEEP. They are not
affected by a WDT Wake-up, since this is viewed as the
resumption of normal operation. TO and PD bits are set
or cleared differently in different RESET situations as
indicated in Table 14-5. These bits are used in software
to determine the nature of the RESET. See Table 14-8
for a full description of RESET states of all registers.
A simplified block diagram of the on-chip RESET circuit
is shown in Figure 14-6.
The MCLR Reset path has a noise filter to detect and
ignore small pulses. See Table 17-6 for pulse width
specification.
FIGURE 14-6:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
S
R
Q
External
RESET
MCLR/
V
DD
OSC1/
WDT
Module
V
DD rise
detect
OST/PWRT
WDT
Timeout
Power-on Reset
OST
PWRT
Chip_Reset
10-bit Ripple-counter
Reset
Enable OST
Enable PWRT
SLEEP
See Table 14-4 for timeout situations.
Note
1:
This is a separate oscillator from the INTRC/ER oscillator.
Brown-out
Detect Reset
BODEN
CLKIN
Pin
V
PP Pin
10-bit Ripple-counter
Q
Schmitt Trigger Input
On-chip(1)
OSC
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