
2003 Microchip Technology Inc.
Preliminary
DS40300C-page 31
PIC16F62X
FIGURE 5-4:
BLOCK DIAGRAM OF RA4/T0CKI PIN
FIGURE 5-5:
BLOCK DIAGRAM OF THE
RA5/MCLR/VPP PIN
FIGURE 5-6:
BLOCK DIAGRAM OF
RA6/OSC2/CLKOUT PIN
Data
Bus
Q
D
Q
CK
N
WR
PORTA
WR
TRISA
Data Latch
TRIS Latch
RD TRISA
RD PORTA
Vss
RA4 Pin
Q
D
Q
CK
D
Q
EN
TMR0 Clock Input
Schmitt Trigger
Input Buffer
Comparator Output
Comparator Mode = 110
1
0
Vss
V
DD
D
Q
EN
HV Detect
MCLR Filter
RA5/MCLR/V
PP
MCLR
Program
MCLRE
RD
V
SS
Data
Bus
V
SS
PORTA
RD
circuit
mode
Schmitt Trigger
Input Buffer
TRISA
WR
D
CK
Q
1
0
PORTA
WR
TRISA
V
DD
V
SS
CLKOUT(F
OSC/4)
(F
OSC =
101, 111) (2)
QD
RD
EN
RD PORTA
F
OSC =
D
CK
Q
100, 110 (1)
TRISA
From OSC1
OSC
Circuit
Note
1: INTRC with RA6 = I/O or ER with RA6 = I/O.
2: INTRC with RA6 = CLKOUT or ER with RA6 = CLK-
OUT.
Schmitt
Trigger
Input Buffer
Data Latch
TRIS Latch