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    • 參數(shù)資料
      型號(hào): PIC16F627-20/P
      廠商: Microchip Technology
      文件頁(yè)數(shù): 6/170頁(yè)
      文件大?。?/td> 0K
      描述: IC MCU FLASH 1KX14 COMP 18DIP
      產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
      8-bit PIC® Microcontroller Portfolio
      標(biāo)準(zhǔn)包裝: 25
      系列: PIC® 16F
      核心處理器: PIC
      芯體尺寸: 8-位
      速度: 20MHz
      連通性: UART/USART
      外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
      輸入/輸出數(shù): 16
      程序存儲(chǔ)器容量: 1.75KB(1K x 14)
      程序存儲(chǔ)器類型: 閃存
      EEPROM 大?。?/td> 128 x 8
      RAM 容量: 224 x 8
      電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
      振蕩器型: 內(nèi)部
      工作溫度: 0°C ~ 70°C
      封裝/外殼: 18-DIP(0.300",7.62mm)
      包裝: 管件
      配用: DVA16XP183-ND - ADAPTER ICE 18DIP/SOIC/SSOP
      AC164010-ND - MODULE SKT PROMATEII DIP/SOIC
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      2003 Microchip Technology Inc.
      Preliminary
      DS40300C-page 101
      PIC16F62X
      14.6
      Interrupts
      The PIC16F62X has 10 sources of interrupt:
      External Interrupt RB0/INT
      TMR0 Overflow Interrupt
      PORTB Change Interrupts (pins RB7:RB4)
      Comparator Interrupt
      USART Interrupt TX
      USART Interrupt RX
      CCP Interrupt
      TMR1 Overflow Interrupt
      TMR2 Match Interrupt
      EEPROM
      The interrupt control register (INTCON) records
      individual interrupt requests in flag bits. It also has
      individual and global interrupt enable bits.
      A global interrupt enable bit, GIE (INTCON<7>)
      enables (if set) all un-masked interrupts or disables (if
      cleared) all interrupts. Individual interrupts can be
      disabled through their corresponding enable bits in
      INTCON register. GIE is cleared on RESET.
      The “return from interrupt” instruction, RETFIE, exits
      interrupt routine as well as sets the GIE bit, which re-
      enable RB0/INT interrupts.
      The INT pin interrupt, the RB port change interrupt and
      the TMR0 overflow interrupt flags are contained in the
      INTCON register.
      The peripheral interrupt flag is contained in the special
      register PIR1. The corresponding interrupt enable bit is
      contained in special registers PIE1.
      When an interrupt is responded to, the GIE is cleared
      to disable any further interrupt, the return address is
      pushed into the stack and the PC is loaded with 0004h.
      Once in the interrupt service routine the source(s) of
      the interrupt can be determined by polling the interrupt
      flag bits. The interrupt flag bit(s) must be cleared in soft-
      ware before re-enabling interrupts to avoid RB0/INT
      recursive interrupts.
      For external interrupt events, such as the INT pin or
      PORTB change interrupt, the interrupt latency will be
      three or four instruction cycles. The exact latency
      depends when the interrupt event occurs (Figure 14-
      15). The latency is the same for one or two cycle
      instructions. Once in the interrupt service routine the
      source(s) of the interrupt can be determined by polling
      the interrupt flag bits. The interrupt flag bit(s) must be
      cleared in software before re-enabling interrupts to
      avoid multiple interrupt requests. Individual interrupt
      flag bits are set regardless of the status of their
      corresponding mask bit or the GIE bit.
      FIGURE 14-14:
      INTERRUPT LOGIC
      Note 1: Individual interrupt flag bits are set
      regardless
      of
      the
      status
      of
      their
      corresponding mask bit or the GIE bit.
      2: When an instruction that clears the GIE
      bit is executed, any interrupts that were
      pending for execution in the next cycle
      are ignored. The CPU will execute a NOP
      in the cycle immediately following the
      instruction which clears the GIE bit. The
      interrupts which were ignored are still
      pending to be serviced when the GIE bit
      is set again.
      TMR2IF
      TMR2IE
      CCP1IF
      CCP1IE
      CMIF
      CMIE
      TXIF
      TXIE
      RCIF
      RCIE
      T0IF
      T0IE
      INTF
      INTE
      RBIF
      RBIE
      GIE
      PEIE
      Wake-up (If in SLEEP mode)
      Interrupt to CPU
      EEIE
      EEIF
      TMR1IF
      TMR1IE
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      參數(shù)描述
      PIC16F627A-E/ML 功能描述:8位微控制器 -MCU 1.75KB 224 RAM 16I/O Ext Temp QFN28 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
      PIC16F627A-E/P 功能描述:8位微控制器 -MCU 1.75KB 224 RAM 16I/O Ext Temp PDIP18 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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      PIC16F627A-E/SS 功能描述:8位微控制器 -MCU 1.75KB 224 RAM 16I/O Ext Temp SSOP20 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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