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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | PIC16F1823-I/P |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋佹暩(sh霉)锛� | 90/109闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MCU 8BIT FLASH 14-DIP |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | 8-bit PIC® Microcontroller Portfolio |
| 鐗硅壊鐢�(ch菐n)鍝侊細 | Extreme Low Power (XLP) Microcontrollers |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 30 |
| 绯诲垪锛� | PIC® XLP™ 16F |
| 鏍稿績铏曠悊鍣細 | PIC |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 32MHz |
| 閫ｉ€氭€э細 | I²C锛孡IN锛孲PI锛孶ART/USART |
| 澶栧湇瑷�(sh猫)鍌欙細 | 娆犲妾㈡脯(c猫)/寰�(f霉)浣嶏紝POR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 12 |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 | 3.5KB锛�2K x 14锛� |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 | 闁冨瓨 |
| EEPROM 澶�?銆�?/td> | 256 x 8 |
| RAM 瀹归噺锛� | 128 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 1.8 V ~ 5.5 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 8x10b |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 14-DIP锛�0.300"锛�7.62mm锛� |
| 鍖呰锛� | 绠′欢 |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�绗�80闋�绗�81闋�绗�82闋�绗�83闋�绗�84闋�绗�85闋�绗�86闋�绗�87闋�绗�88闋�绗�89闋�鐣�(d膩ng)鍓嶇90闋�绗�91闋�绗�92闋�绗�93闋�绗�94闋�绗�95闋�绗�96闋�绗�97闋�绗�98闋�绗�99闋�绗�100闋�绗�101闋�绗�102闋�绗�103闋�绗�104闋�绗�105闋�绗�106闋�绗�107闋�绗�108闋�绗�109闋�
2010-2012 Microchip Technology Inc.
DS41413C-page 41
PIC12(L)F1822/PIC16(L)F1823
Bank 31
F80h(1)
INDF0
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
F81h(1)
INDF1
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
F82h(1)
PCL
Program Counter (PC) Least Significant Byte
0000 0000 0000 0000
F83h(1)
STATUS
鈥�
鈥擳O
PD
ZDC
C
---1 1000 ---q quuu
F84h(1)
FSR0L
Indirect Data Memory Address 0 Low Pointer
0000 0000 uuuu uuuu
F85h(1)
FSR0H
Indirect Data Memory Address 0 High Pointer
0000 0000 0000 0000
F86h(1)
FSR1L
Indirect Data Memory Address 1 Low Pointer
0000 0000 uuuu uuuu
F87h(1)
FSR1H
Indirect Data Memory Address 1 High Pointer
0000 0000 0000 0000
F88h(1)
BSR
鈥�
BSR<4:0>
---0 0000 ---0 0000
F89h(1)
WREG
Working Register
0000 0000 uuuu uuuu
F8Ah(1)
PCLATH
鈥�
Write Buffer for the upper 7 bits of the Program Counter
-000 0000 -000 0000
F8Bh(1)
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
0000 000x 0000 000u
F8Ch
鈥�
FE3h
鈥�
Unimplemented
鈥�
FE4h
STATUS_
SHAD
鈥�
Z_SHAD
DC_SHAD
C_SHAD ---- -xxx ---- -uuu
FE5h
WREG_
SHAD
Working Register Shadow
0000 0000 uuuu uuuu
FE6h
BSR_
SHAD
鈥�
Bank Select Register Shadow
---x xxxx ---u uuuu
FE7h
PCLATH_
SHAD
鈥�
Program Counter Latch High Register Shadow
-xxx xxxx uuuu uuuu
FE8h
FSR0L_
SHAD
Indirect Data Memory Address 0 Low Pointer Shadow
xxxx xxxx uuuu uuuu
FE9h
FSR0H_
SHAD
Indirect Data Memory Address 0 High Pointer Shadow
xxxx xxxx uuuu uuuu
FEAh
FSR1L_
SHAD
Indirect Data Memory Address 1 Low Pointer Shadow
xxxx xxxx uuuu uuuu
FEBh
FSR1H_
SHAD
Indirect Data Memory Address 1 High Pointer Shadow
xxxx xxxx uuuu uuuu
FECh
鈥�
Unimplemented
鈥�
FEDh
STKPTR
鈥�
Current Stack pointer
---1 1111 ---1 1111
FEEh
TOSL
Top-of-Stack Low byte
xxxx xxxx uuuu uuuu
FEFh
TOSH
鈥�
Top-of-Stack High byte
-xxx xxxx -uuu uuuu
TABLE 3-8:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Legend:
x
= unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as 鈥�0鈥�.
Note
1:
These registers can be addressed from any bank.
2:
PIC16(L)F1823 only.
3:
Unimplemented. Read as 鈥�1鈥�.
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| PIC16F1823T-I/ML | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 3.5KB 128B RAM 32MHz Int. Osc 12 I/0 RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| PIC16F1823T-I/SL | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 3.5KB 128B RAM 32MHz Int. Osc 12 I/0 RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| PIC16F1823T-I/ST | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 3.5KB 128B RAM 32MHz Int. Osc 12 I/0 RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| PIC16F1824-E/ML | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 7KB Flash 256b RAM 32 MHz Int. Osc RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| PIC16F1824-E/P | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 7KB Flash 256b RAM 32 MHz Int. Osc RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
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