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參數(shù)資料
| 型號： | PIC16F1527-I/PT |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 14/94頁 |
| 文件大小： | 0K |
| 描述： | MCU 28KB FLASH 1536B RAM 64-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Configurable Logic Cell 8-bit PIC® Microcontroller Portfolio |
| 特色產(chǎn)品： | Extreme Low Power (XLP) Microcontrollers |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 系列： | PIC® XLP™ 16F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 連通性： | I²C，LIN，SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 54 |
| 程序存儲器容量： | 28KB（16K x 14） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1.5K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.3 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 30x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 64-TQFP |
| 包裝： | 托盤 |
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183
7810C–AVR–10/12
Atmel ATmega328P [Preliminary]
Figure 19-6. Sampling of Data and Parity Bit
The decision of the logic level of the received bit is taken by doing a majority voting of the logic
value to the three samples in the center of the received bit. The center samples are emphasized
on the figure by having the sample number inside boxes. The majority voting process is done as
follows: If two or all three samples have high levels, the received bit is registered to be a logic 1.
If two or all three samples have low levels, the received bit is registered to be a logic 0. This
majority voting process acts as a low pass filter for the incoming signal on the RxDn pin. The
recovery process is then repeated until a complete frame is received. Including the first stop bit.
Note that the Receiver only uses the first stop bit of a frame.
Figure 19-7 on page 183 shows the sampling of the stop bit and the earliest possible beginning
of the start bit of the next frame.
Figure 19-7. Stop Bit Sampling and Next Start Bit Sampling
The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop
bit is registered to have a logic 0 value, the Frame Error (FEn) Flag will be set.
A new high to low transition indicating the start bit of a new frame can come right after the last of
the bits used for majority voting. For Normal Speed mode, the first low level sample can be at
point marked (A) in Figure 19-7. For Double Speed mode the first low level must be delayed to
(B). (C) marks a stop bit of full length. The early start bit detection influences the operational
range of the Receiver.
19.8.3
Asynchronous Operational Range
The operational range of the Receiver is dependent on the mismatch between the received bit
rate and the internally generated baud rate. If the Transmitter is sending frames at too fast or too
slow bit rates, or the internally generated baud rate of the Receiver does not have a similar (see
Table 19-2 on page 184) base frequency, the Receiver will not be able to synchronize the
frames to the start bit.
12
34
56
7
8
9
10
11
12
13
14
15
16
1
BIT n
123
4
5
678
1
RxD
Sample
(U2X = 0)
Sample
(U2X = 1)
12
34
56
7
8
9
10
0/1
STOP 1
123
4
5
6
0/1
RxD
Sample
(U2X = 0)
Sample
(U2X = 1)
(A)
(B)
(C)
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| PIC16F1527T-I/MR | 功能描述:8位微控制器 -MCU 28KB FL 1536B RAM 10bit ADC 1.8-5.5V RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| PIC16F1527T-I/PT | 功能描述:8位微控制器 -MCU 14KB Flash RAM 768b nanoWatt RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| PIC16F1613-E/P | 制造商:Microchip Technology Inc 功能描述:3.5KB Flash, 256 RAM, 32MHz Int. Osc, 10bit ADC, ZCD, WWDT, CRC, 14 PDIP .300in |
| PIC16F1613-I/SL | 制造商:Microchip Technology Inc 功能描述:3.5KB FLASH, 256 RAM, 32MHZ INT. OSC, 10BIT ADC, ZCD, WWDT, - Rail/Tube |
| PIC16F1613-I/ST | 制造商:Microchip Technology Inc 功能描述:3.5KB FLASH, 256 RAM, 32MHZ INT. OSC, 10BIT ADC, ZCD, WWDT, - Rail/Tube |
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