參數(shù)資料
型號(hào): PIC16F1526-I/PT
廠商: Microchip Technology
文件頁(yè)數(shù): 79/94頁(yè)
文件大?。?/td> 0K
描述: MCU 14KB FLASH 768B RAM 64-TQFP
產(chǎn)品培訓(xùn)模塊: Configurable Logic Cell
8-bit PIC® Microcontroller Portfolio
特色產(chǎn)品: Extreme Low Power (XLP) Microcontrollers
標(biāo)準(zhǔn)包裝: 160
系列: PIC® XLP™ 16F
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C,LIN,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 54
程序存儲(chǔ)器容量: 14KB(8K x 14)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 768 x 8
電壓 - 電源 (Vcc/Vdd): 2.3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 30x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 托盤
PIC16(L)F1526/27
DS41458B-page 46
Preliminary
2011 Microchip Technology Inc.
REGISTER 4-1:
CONFIGURATION WORD 1
R/P-1
U-1
FCMEN
IESO
CLKOUTEN
BOREN<1:0>
bit 13
bit 8
R/P-1
CP
MCLRE
PWRTE
WDTE<1:0>
FOSC<2:0>
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared
‘1’ = Bit is set
-n = Value when blank or after Bulk Erase
bit 13
FCMEN:
Fail-Safe Clock Monitor Enable bit
1
= Fail-Safe Clock Monitor is enabled
0
= Fail-Safe Clock Monitor is disabled
bit 12
IESO:
Internal External Switchover bit
1
= Internal/External Switchover mode is enabled
0
= Internal/External Switchover mode is disabled
bit 11
CLKOUTEN:
Clock Out Enable bit
If FOSC configuration bits are set to LP, XT, HS modes:
This bit is ignored, CLKOUT function is disabled. Oscillator function on the CLKOUT pin.
All other FOSC modes:
1
= CLKOUT function is disabled. I/O function on the CLKOUT pin.
0
= CLKOUT function is enabled on the CLKOUT pin
bit 10-9
BOREN<1:0>:
Brown-out Reset Enable bits
11
= BOR enabled
10
= BOR enabled during operation and disabled in Sleep
01
= BOR controlled by SBOREN bit of the BORCON register
00
= BOR disabled
bit 8
Unimplemented:
Read as ‘1’
bit 7
CP:
Code Protection bit
1
= Program memory code protection is disabled
0
= Program memory code protection is enabled
bit 6
MCLRE:
MCLR/VPP Pin Function Select bit
If LVP bit = 1:
This bit is ignored.
If LVP bit = 0:
1
=MCLR/VPP pin function is MCLR; Weak pull-up enabled.
0
=MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of
WPUE3 bit.
bit 5
PWRTE:
Power-up Timer Enable bit
1
= PWRT disabled
0
= PWRT enabled
bit 4-3
WDTE<1:0>:
Watchdog Timer Enable bit
11
= WDT enabled
10
= WDT enabled while running and disabled in Sleep
01
= WDT controlled by the SWDTEN bit in the WDTCON register
00
= WDT disabled
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